The Community for Technology Leaders
27th Annual Simulation Symposium (1994)
La Jolla, CA, USA
April 11, 1994 to April 15, 1994
ISBN: 0-8186-5620-4
TABLE OF CONTENTS

Application of a redefinable symbolic simulation technique in VLSI testability design rules checking (PDF)

M. Hirech , Lab. MASI, Univ. Pierre et Marie Curie, Paris, France
O. Florent , Lab. MASI, Univ. Pierre et Marie Curie, Paris, France
A. Greiner , Lab. MASI, Univ. Pierre et Marie Curie, Paris, France
E. Rejouan , Lab. MASI, Univ. Pierre et Marie Curie, Paris, France
pp. 255-261

DIPART, an interactive simulation platform for studying plan development and monitoring in dynamic environments (PDF)

T.F. Znati , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
M.E. Pollack , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
pp. 236-244

Low cost load balancing algorithms (PDF)

Weiping Zhu , Sch. of Comput. & Inf. Sci., Univ. South Australia, Adelaide, SA, Australia
pp. 226-235

Design and simulation of hard real-time applications (PDF)

Jiang Zhu , Dept. of Comput. Sci., Oregon State Univ., Corvallis, OR, USA
Lihua Zhao , Dept. of Comput. Sci., Oregon State Univ., Corvallis, OR, USA
pp. 217-225

VLSI timing simulation with selective dynamic regionization (PDF)

Meng-Lin Yu , AT&T Bell Labs., Holmdel, NJ, USA
B.D. Ackland , AT&T Bell Labs., Holmdel, NJ, USA
pp. 208-216

OPERAS/spl minus/an object-oriented signal processing system architecture simulator (PDF)

G.K. Yeh , Dept. of Electr. Eng., Stanford Univ., CA, USA
K. Bagchi , Dept. of Electr. Eng., Stanford Univ., CA, USA
J.B. Burr , Dept. of Electr. Eng., Stanford Univ., CA, USA
A.M. Peterson , Dept. of Electr. Eng., Stanford Univ., CA, USA
pp. 198-207

SimTool, an object oriented simulation environment (PDF)

M.E. Yazbeck , LinCom Corp., Houston, TX, USA
E.Z. Crues , LinCom Corp., Houston, TX, USA
H.C. Edwards , LinCom Corp., Houston, TX, USA
R.D. Barnette , LinCom Corp., Houston, TX, USA
pp. 188-197

Simulation analysis of a dynamic checkpointing strategy for real-time systems (PDF)

A. Ranganathan , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
S.J. Upadhyaya , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
pp. 181-187

Object-oriented design of a scene generation simulation (PDF)

F. Wieland , Naval Res. Lab., Washington, DC, USA
H. Heckathorn , Naval Res. Lab., Washington, DC, USA
pp. 174-180

A novel approximation procedure for efficient yield simulation and optimization of integrated circuits (PDF)

Zhihua Wang , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
S.W. Director , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 166-173

Foresight: system simulation for system developers (PDF)

M.D. Vertal , Nu Thena Syst. Inc., McLean, VA, USA
pp. 156-165

Comparison of time-step sizes for stability and convergence in transient analysis of MOSFET circuits (PDF)

Ching-Chuan Su , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 150-155

Fault-tolerance of a MIN using hybrid redundancy (PDF)

N.K. Sharma , Dept. of Comput. Sci. & Comput. Eng., La Trobe Univ., Melbourne, Vic., Australia
pp. 142-149

A flexible technique for OS-support in instruction level simulators (PDF)

B. Roslund , Dept. of Comput. Eng., Lund Univ., Sweden
P. Andersson , Dept. of Comput. Eng., Lund Univ., Sweden
pp. 134-141

Simulating networks of superscalar processors (PDF)

E. Reiher , CRIM, McGill Coll., Montreal, Que., Canada
pp. 125-133

PARSE: simulation of message passing communication networks (PDF)

E. Olk , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 115-124

Cyclo-static multiprocessing model and simulation results (PDF)

Sukhamoy Som , Lockheed Eng. & Sci. Co., Hampton, VA, USA
pp. 106-114

Ordered ternary decision diagrams and the multivalued compiled simulation of unmapped logic (PDF)

G. Jennings , Div. of Comput. Eng., Lulea Inst. of Technol., Sweden
J. Isaksson , Div. of Comput. Eng., Lulea Inst. of Technol., Sweden
P. Lindgren , Div. of Comput. Eng., Lulea Inst. of Technol., Sweden
pp. 99-105

Simulating a multiple segment LAN (PDF)

A.R. Hajare , Enhanced Technol., Houston, TX, USA
pp. 89-98

XPOSE: a simulator for network development (PDF)

D. Zukowski , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
M. Gupta , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
M. Gopal , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
N. Budhiraja , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 59-69

The resolution of an open-loop resource allocation problem using a neural network approach (PDF)

J. Berger , Command & Control Div., Defence Res. Establ. Valcartier, Courcelette, Que., Canada
pp. 51-58

Performance evaluation of a multimedia server for ATM networks (PDF)

G. Damm , Dept. Inf., Inst. Nat. des Telecommun., Evry, France
pp. 41-50

A methodology for evaluating parallel I/O performance for massively parallel processors (PDF)

S. Johnson Baylor , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
C. Benveniste , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 31-40

Delay-time bounds and waveform bounds for RLCG ladder networks (PDF)

Ying-Wen Bai , Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
C.A. Zukowski , Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
pp. 23-30

Parallel simulation of heterogeneous arithmetic units networks and high precision dot products (PDF)

M. Fiallos Aguilar , Lab. LIP, Ecole Normale Superieure de Lyon, France
J. Duprat , Lab. LIP, Ecole Normale Superieure de Lyon, France
pp. 13-22

The Maisie environment for parallel simulation (PDF)

R.L. Bagrodia , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
V. Jha , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
J. Waldorf , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 4-12
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