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Memory Technology, Design and Testin, IEEE International Workshop on (1996)
Aug. 13, 1996 to Aug. 14, 1996
ISBN: 0-8186-7466-0
Keynote Speech I
Session 1: Review Paper I

Recent developments in dram testing (PDF)

B.F. Cockburn , University of Alberta
pp. 0006
Session 2: Testing I

Built in self testing for detection of coupling faults in semiconductor memories (Abstract)

M.G. Karpovsky , Boston University
D. Das , Boston University
H. Vardhan , Boston University
pp. 0008

A built in self test scheme for 256Meg sdram (Abstract)

F. Hii , Texas Instruments
T. Powell , Texas Instruments
D. Cline , Texas Instruments
pp. 0015
Session 3: Design and Technology I

Flash memory quality and reliability issues (Abstract)

R. Verma , Intel Corporation
pp. 0032

A low power current sensing scheme for cmos sram (Abstract)

H. Wang , Nanyang Technological University
P.C. Liu , Nanyang Technological University
pp. 0037
Session 4: Review Papers II
Session 5: Testing II

Methods for memory test time reduction (Abstract)

Wen-Jer Wu , National Tsing-Hua University
Chuan Yi Tang , National Tsing-Hua University
M.Y. Lin , National Tsing-Hua University
pp. 0064
Session 6: Design and Technology II

Design and analysis of a synchronous dram memory module (Abstract)

G. Ley , Texas Instruments
D. Phipps , Texas Instruments
pp. 0072

Scanning capacitance microscopy analysis of dram trench capacitors (Abstract)

K.L. Pey , Institute of Microelectronics
Y.E. Strausser , Institute of Microelectronics
A.N. Erickson , Institute of Microelectronics
A.J. Leslie , Institute of Microelectronics
M.T.F. Beh , Institute of Microelectronics
T.T. Sheng , Institute of Microelectronics
pp. 0079

Thermal monitoring of memories (Abstract)

V. Szekely , Technical University of Budapest
B. Courtois , Technical University of Budapest
pp. 0086
Session 7: Testing III

RAM diagnostic tests (Abstract)

V.N. Yarmolik , Belarusian State University
Yu.V. Klimets , Belarusian State University
A.J. van de Goor , Belarusian State University
S.N. Demidenko , Belarusian State University
pp. 0100

A true testprocessor-per-pin algorithmic pattern generator (Abstract)

K. Hilliges , Hewlett Packard GmbH
J. Sundermann , Hewlett Packard GmbH
pp. 0103

Design-for-test analysis of a buffered sdram dimm (Abstract)

S. Jandhyala , Texas Instruments
A. Ley , Texas Instruments
pp. 0110

Author Index (PDF)

pp. 0117
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