The Community for Technology Leaders
1993 IEEE International Workshop on Memory Testing (1993)
San Jose, CA, USA
Aug. 9, 1993 to Aug. 10, 1993
ISBN: 0-8186-4150-9
TABLE OF CONTENTS

A current testing for CMOS static RAMs (PDF)

H. Yokoyama , Dept. of Inf. Eng., Akita Univ., Japan
H. Tamamoto , Dept. of Inf. Eng., Akita Univ., Japan
Y. Narita , Dept. of Inf. Eng., Akita Univ., Japan
pp. 137-142

Automatic verification of march tests (SRAMs) (PDF)

A.J. van de Goor , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
B. Smit , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 131-136

Dynamic reconfiguration schemes for mega bit BiCMOS SRAMs (PDF)

V.N. Rayapati , Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
B. Kaminska , Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
pp. 125-130

Total dose radiation hardening and testing issues of CMOS static memories (PDF)

R. Hensley , Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA
A. Srivastava , Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA
pp. 108-112

Are NV-memories non-volatile? (PDF)

D. Ratchev , Reliability Lab, Swiss Federal Inst. of Technol., Zurich, Switzerland
pp. 102-106

An inexpensive method of detecting localised parametric defects in static RAM (PDF)

Y. Savaria , Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
pp. 90-95

Modeling of intra-cell defects in CMOS SRAM (PDF)

W.K. Al-Assadi , Colorado State Univ., Fort Collins, CO, USA
Y.K. Malaiya , Colorado State Univ., Fort Collins, CO, USA
A.P. Jayasumana , Colorado State Univ., Fort Collins, CO, USA
pp. 78-81

Fault models and tests specific for FIFO functionality (PDF)

A.J. van de Goor , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 72-76

An optimal march test for locating faults in DRAMs (PDF)

Lin Shen , Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
B.F. Cockburn , Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
pp. 61-66

Fault location algorithms for repairable embedded RAMs (PDF)

R. Treuer , Dept. Electr. Eng., McGill Univ., Montreal, Que., Canada
V.K. Agarwal , Dept. Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 55-60

Algorithms to test PSF and coupling faults in random access memories (PDF)

R. Rajsuman , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
pp. 49-54

Functional testing of RAMs by random testing simulation (PDF)

M. Ashtijou , Dept. of Electr. Eng., Texas A&I Univ., Kingsville, TX, USA
Fusheng Chen , Dept. of Electr. Eng., Texas A&I Univ., Kingsville, TX, USA
pp. 44-48

Associative search based test algorithms for test acceleration in FAST-RAMs (PDF)

C. Elm , Fern Univ. Hagen, Tech. Informatik II, Germany
D. Tavangarian , Fern Univ. Hagen, Tech. Informatik II, Germany
pp. 38-43

Modeling of faulty behavior of ECL storage elements (PDF)

S.M. Menon , Colorado State Univ., Ft. Collins, CO, USA
Y.K. Malaiya , Colorado State Univ., Ft. Collins, CO, USA
A.P. Jayasumana , Colorado State Univ., Ft. Collins, CO, USA
pp. 31-36

On-line and off-line testable design of random access memories (PDF)

S. Subramanian , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 26-30

Exact aliasing computation and/or aliasing free design for RAM BIST (PDF)

V.N. Yarmolik , TIMA/INPG, Grenoble, France
M. Nicolaidis , TIMA/INPG, Grenoble, France
pp. 20-25

PLA test pattern generation with orthogonal transform (PDF)

M.W. Riege , Electron. Dept., Bremen Univ., Germany
S. Wolter , Electron. Dept., Bremen Univ., Germany
W. Anheier , Electron. Dept., Bremen Univ., Germany
pp. 15-18

A 20 MHz test vector generator for producing tests that detect single 4- and 5-coupling faults in RAMs (PDF)

B.F. Cockburn , Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
pp. 10-14

A high-speed boundary search Shmoo plot for ULSI memories (PDF)

M. Hamada , LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
M. Kumanoya , LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
M. Ishii , LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
T. Kawagoe , LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
M. Niiro , LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
pp. 4-9
96 ms
(Ver 3.3 (11022016))