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Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) (1994)
San Francisco, CA, USA
Jan. 19, 1994 to Jan. 21, 1994
ISBN: 0-7803-1850-1
TABLE OF CONTENTS

Quasi-analytical analysis of the broadband properties of multiconductor transmission lines on semiconducting substrates (PDF)

E. Groteluschen , Lab. fur Informationstechnol., Hannover Univ., Germany
L.S. Dutta , Lab. fur Informationstechnol., Hannover Univ., Germany
pp. 387-399

Optimal chip sizing for hybrid-WSI (PDF)

P. Singh , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
D.L. Landis , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
pp. 374-386

A single-chip digital signal processing system (PDF)

J.E. Brewer , Westinghouse Electr. Corp., USA
L.G. Miller , Westinghouse Electr. Corp., USA
pp. 265-272

Integrated diagnosis and reconfiguration process for defect tolerant WSI processor arrays (PDF)

Kuochen Wang , Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jenn-Wei Lin , Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 198-207

Image processing using a universal nonlinear cell (PDF)

V.K. Jain , Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
L. Lin , Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
pp. 40-51

An efficient method to reduce roundoff error in matrix multiplication with algorithm-based fault tolerance (PDF)

Qihong Zhang , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
J.H. Kim , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
pp. 32-39

Silicon wafer-area network: intelligent communications fabric for parallel computing (PDF)

I.V. Petrova , Dept. of Electr. & Comput. Eng., West Virginia Univ., Morgantown, WV, USA
M.T. Uppuluri , Dept. of Electr. & Comput. Eng., West Virginia Univ., Morgantown, WV, USA
S.K. Tewksbury , Dept. of Electr. & Comput. Eng., West Virginia Univ., Morgantown, WV, USA
L.A. Hornak , Dept. of Electr. & Comput. Eng., West Virginia Univ., Morgantown, WV, USA
pp. 362-373

Comparison of laser link crossbar and Omega network switching for wafer-scale integration defect avoidance (PDF)

G.H. Chapman , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
K. Fang , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 352-361

WSI design of a radix 2 butterfly using macrocell pools (PDF)

T.K. Callaway , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 342-351

Fault tolerant multicube pipeline processor (PDF)

H. Mori , Dept. of Inf. & Comput. Sci., Toyo Univ., Japan
M. Uehara , Dept. of Inf. & Comput. Sci., Toyo Univ., Japan
pp. 334-341

Integration scale increase of processor-arrays by using hierarchical redundancy (PDF)

N. Tsuda , NTT Network Inf. Syst. Labs., Tokyo, Japan
pp. 324-333

Test and reconfiguration experiments for a defect-tolerant large area monolithic multiprocessor system (PDF)

J. Otterstedt , Lab. fur Informationstechnologie, Hannover Univ., Germany
H.-J. Iden , Lab. fur Informationstechnologie, Hannover Univ., Germany
M. Kuboschek , Lab. fur Informationstechnologie, Hannover Univ., Germany
pp. 315-323

Optimizing reliability in a two-level distributed architecture for wafer scale integration (PDF)

J.R. Samson , Space & Strategic Syst. Oper., Honeywell Inc., Clearwater, FL, USA
pp. 292-314

Wafer-scale integration as a technology choice for high speed ATM switching systems (PDF)

N. Mirfakhraei , Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA
pp. 282-291

Design of a large area magnetic field sensor array (PDF)

Y. Audet , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
G.H. Chapman , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 273-281

Clock synchronization for WSI systems (PDF)

S.H.K. Embabi , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
D.E. Brueske , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 228-234

Reducing cost and ensuring on-time delivery of hybrid-WSI massively parallel computing modules (PDF)

C.M. Habiger , Aspex Microsyst. Ltd., Brunel Univ., Uxbridge, UK
R.M. Lea , Aspex Microsyst. Ltd., Brunel Univ., Uxbridge, UK
pp. 218-227

Design for diagnosability and diagnostic strategies of WSI array architectures (PDF)

Kuochen Wang , Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Wang-Dauh Tseng , Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 208-217

Diagnosis of reconfigurable two-dimensional arrays using a scan approach (PDF)

J. Salinas , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
F. Lombardi , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 179-187

Design for testability issues in the implementation of sequential array architectures (PDF)

G. Bezzi , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
C. Bolchini , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
I. Bolzoni , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
S. Cantu , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
F. Fummi , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
D. Sciuto , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
pp. 169-178

WSI evolution: increasing cell size to generalize designs (PDF)

S.D. Millman , Motorola Inc., Tempe, AZ, USA
pp. 163-168

Optimal reconfiguration of WSI multipipeline arrays (PDF)

J. Salinas , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
C. Feng , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
J. Wall , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
F. Lombardi , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 143-152

Reconfigurable fault tolerant binary tree-implementation in two-dimensional arrays and reliability analysis (PDF)

I. Takanami , Dept. of Comput. Sci. & Syst. Eng., Yamaguchi Univ., Ube, Japan
K. Inoue , Dept. of Comput. Sci. & Syst. Eng., Yamaguchi Univ., Ube, Japan
T. Watanabe , Dept. of Comput. Sci. & Syst. Eng., Yamaguchi Univ., Ube, Japan
pp. 132-142

What designers of wafer scale systems should know about local sparing (PDF)

L.E. LaForge , Dept. of Electr. Eng., Nevada Univ., Reno, NV, USA
pp. 106-131

A computer-aided tool for multichip module package design (PDF)

P. Katragadda , Dept. of Mech. Eng., Massachusetts Univ., Amherst, MA, USA
S. Bhattacharya , Dept. of Mech. Eng., Massachusetts Univ., Amherst, MA, USA
I.R. Grosse , Dept. of Mech. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 92-105

The effect of defect clustering on WASP device yields (PDF)

C. Peacock , Eng. Res. & Dev. Centre, Hertfordshire Univ., Hatfield, UK
H. Bolouri , Eng. Res. & Dev. Centre, Hertfordshire Univ., Hatfield, UK
pp. 79-91

Harvest model of an integrated hierarchical-bus architecture (PDF)

R. Kermouche , Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
Y. Savaria , Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
pp. 69-78

Yield enhancement architecture of WSI cube-connected cycle (PDF)

S. Horiguchi , Graduate Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
S. Fukuda , Graduate Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
pp. 61-68

Yield enhancement in the routing phase of integrated circuit layout synthesis (PDF)

A. Tyagi , Dept. of Electr. & Comput. Eng., Southwestern Louisiana Univ., Lafayette, LA, USA
pp. 52-60

3D-WASP devices for on-line signal and data processing (PDF)

S.J. Hedge , Aspex Microsyst., Brunel Univ., Uxbridge, UK
C.M. Habiger , Aspex Microsyst., Brunel Univ., Uxbridge, UK
R.M. Lea , Aspex Microsyst., Brunel Univ., Uxbridge, UK
pp. 11-21

Test vehicle for a wafer-scale thermal pixel scene simulator (PDF)

G.H. Chapman , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
L. Carr , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
M.J. Syrzycki , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
B. Dufort , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 1-10
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