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1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon (1996)
Austin, TX, USA
Oct. 9, 1996 to Oct. 11, 1996
ISSN: 1063-2204
ISBN: 0-7803-3639-9
TABLE OF CONTENTS

A VLSI architecture for an 80 Gb/s ATM switch core (PDF)

P. Andersson , Dept. of Comput. Eng., Lund Univ., Sweden
pp. 9-15

A VLSI inner product macrocell (PDF)

L. Breveglieri , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
pp. 26-35

The quasi-Booth multiplier (PDF)

L. Dadda , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
pp. 36-45

Towards an integrated sub-nanogram mass measurement system (PDF)

B. Ghodsian , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 71-80

Reconfigurable analog integrated circuit architecture based on switched-capacitor techniques (PDF)

E.K.F. Lee , Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 148-158

Survey of low power techniques for VLSI design (PDF)

E. De Angel , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 159-169

A conceptual analysis framework for low power design of embedded systems (PDF)

W. Fornaciari , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
pp. 170-179

Testability and signal integrity in a low cost multichip module (PDF)

A. Omer , Semicond. Products, Motorola Inc., Austin, TX, USA
pp. 189-197

Multichip module yield enhancement using passive substrate fault tolerance (PDF)

C. Peacock , Eng. Res. & Dev. Centre, Hertfordshire Univ., Hatfield, UK
pp. 198-209

Early analysis of cost/performance trade-offs in MCM systems (PDF)

V. Garg , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 228-237

Array-based testing of FPGAs: architecture and complexity (PDF)

W.K. Huang , Dept. of Electron. Eng., Fudan Univ., Shanghai, China
pp. 249-258

Testability analysis of pipelined data paths (PDF)

G. Buonanno , Dept. of Electron. & Inf., Politecnico di Milano, Italy
pp. 259-268

Yield analysis of a novel scheme for defect-tolerant memories (PDF)

I. Koren , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 269-278

Fast yield prediction for accurate costing of ICs (PDF)

G.A. Allan , Dept. of Electr. Eng., Edinburgh Univ., UK
pp. 279-287

Feasible regions quantify the probabilistic configuration power of arrays with multiple fault types (PDF)

L.E. LaForge , Embry-Riddle Aeronaut. Univ., Fallon Naval Air Station, NV, USA
pp. 298-312

CostAS-KGD process cost modeling (PDF)

D. Ammann , Electron. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
pp. 313-322

MCM-L as a cost-effective solution for high-speed digital design (PDF)

A. Thiel , Electron. Lab., Eidgenossische Tech. Hochschule, Zurich, Switzerland
pp. 330-340

Use of multi-port memories in programmable structures for architectural synthesis (PDF)

C. Mandal , Dept. of Comput. Sci., Brunel Univ., Uxbridge, UK
pp. 341-351

Reduced complexity SIMD-class architectures (PDF)

M.A. Glover , Current Technol., Durham, NH, USA
pp. 352-361

Fault-tolerant cube-connected cycles capable of quick broadcasting (PDF)

N. Tsuda , Inf. & Commun. Syst. Labs., NTT, Tokyo, Japan
pp. 362-371

VLSI architecture of a scalable matrix transposer (PDF)

O. Fatemi , Dept. of Electr. Eng., Ottawa Univ., Ont., Canada
pp. 382-391
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