The Community for Technology Leaders
2006 24th International Conference on Computer Design (2006)
San Jose, CA
Oct. 1, 2006 to Oct. 4, 2006
ISSN: 1063-6404
ISBN: 978-0-7803-9706-4
TABLE OF CONTENTS

Welcome to ICCD 2006! (PDF)

pp. xii-xiii

Long-term Performance Bottleneck Analysis and Prediction (PDF)

Fei Gao , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695. Email: fgao@ncsu.edu
Suleyman Sair , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695. Email: ssair@ncsu.edu
pp. 3-9

Dynamic Code Value Specialization Using the Trace Cache Fill Unit (PDF)

Weifeng Zhang , Department of Computer Science and Engineering, University of California, San Diego
Steve Checkoway , Department of Computer Science and Engineering, University of California, San Diego
Brad Calder , Department of Computer Science and Engineering, University of California, San Diego
Dean M. Tullsen , Department of Computer Science and Engineering, University of California, San Diego
pp. 10-16

Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses (Abstract)

Jiangjiang Liu , Dept. of Comp. Sci., Lamar University, Beaumont, TX 77710, U. S. A. E-mail: liu@cs.lamar.edu
Krishnan Sundaresan , Dept. of Elect. & Comp. Eng., Michigan State University, East Lansing, MI 48824, U. S. A. E-mail: sundare2@egr.msu.edu
Nihar R. Mahapatra , Dept. of Elect. & Comp. Eng., Michigan State University, East Lansing, MI 48824, U.S.A. E-mail: nrm@egr.msu.edu
pp. 17-24

Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft Indexing (PDF)

Shuo Wang , Department of Electrical and Computer Engineering, University of Connecticut, 371 Fairfield Road, U-2157, Storrs, CT 06269. Email: shuo.wang@engr.uconn.edu
Lei Wang , Department of Electrical and Computer Engineering, University of Connecticut, 371 Fairfield Road, U-2157, Storrs, CT 06269. Email: leiwang@engr.uconn.edu
pp. 25-30

A Low Power Highly Associative Cache for Embedded Systems (PDF)

Chuanjun Zhang , Department of Computer Science and Electrical Engineering, University of Missouri-Kansas City. zhangchu@umkc.edu
pp. 31-36

On the Improvement of Statistical Timing Analysis (Abstract)

Rajesh Garg , Department of Electrical & Computer Engineering, Texas A&M University, College Station TX 77843. rajeshgarg_at_tamu.edu
Nikhil Jayakumar , Department of Electrical & Computer Engineering, Texas A&M University, College Station TX 77843. nikhil_at_ece.tamu.edu
Sunil P Khatri , Department of Electrical & Computer Engineering, Texas A&M University, College Station TX 77843. sunilkhatri_at_tamu.edu
pp. 37-42

FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling (PDF)

Debasish Das , EECS, Northwestern University, Evanston, IL 60208
Ahmed Shebaita , EECS, Northwestern University, Evanston, IL 60208
Hai Zhou , EECS, Northwestern University, Evanston, IL 60208
Yehea Ismail , EECS, Northwestern University, Evanston, IL 60208
Kip Killpack , Strategic CAD Lab, Intel Corporation, Hillsboro, OR 97124
pp. 43-49

Reduction of Crosstalk Pessimism Using Tendency Graph Approach (PDF)

Murthy Palla , Future Design Systems Group, Infineon Technologies AG, Munich. murthy.palla@infineon.com
Klaus Koch , Future Design Systems Group, Infineon Technologies AG, Munich. klaus.koch@infineon.com
Jens Bargfrede , Future Design Systems Group, Infineon Technologies AG, Munich. jens.bargfrede@infineon.com
Manfred Glesner , Institute of Microelectronic Systems, Darmstadt University of Technology, Darmstadt, glesner@mes.tu-darmstadt.de
Walter Anheier , ITEM, University of Bremen, Bremen, anheier@item.uni-bremen.de
pp. 50-55

Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation (PDF)

Ning Mi , Student Member, IEEE, Department of Electrical Engineering, University of California, Riverside, CA 92521, USA
Jeffrey Fan , Student Member, IEEE, Department of Electrical Engineering, University of California, Riverside, CA 92521, USA
Sheldon X.-D. Tan , Senior Member, IEEE, Department of Electrical Engineering, University of California, Riverside, CA 92521, USA
pp. 56-62

RasP: An Area-efficient, On-chip Network (Abstract)

Simon Hollis , Computer Laboratory, University of Cambridge, Cambridge, CB3 0FD, UK. Email: Simon.Hollis@cl.cam.ac.uk
Simon W. Moore , Computer Laboratory, University of Cambridge, Cambridge, CB3 0FD, UK. Email: Simon.Moore@cl.cam.ac.uk
pp. 63-69

Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects (PDF)

Yasuhiro Ogasahara , Dept. Information Systems Engineering, Osaka University, Suita 565-0871, JAPAN. ogshr@ist.osaka-u.ac.jp
Masanori Hashimoto , Dept. Information Systems Engineering, Osaka University, Suita 565-0871, JAPAN. hasimoto@ist.osaka-u.ac.jp
Takao Onoye , Dept. Information Systems Engineering, Osaka University, Suita 565-0871, JAPAN. onoye@ist.osaka-u.ac.jp
pp. 70-75

CMOS Comparators for High-Speed and Low-Power Applications (Abstract)

Eric R. Menendez , Department of CSE, The Pennsylvania State University, University Park, PA 16802
Dumezie K. Maduike , Department of ECE, Rutgers University, New Brunswick, NJ 08854
Rajesh Garg , Department of ECE, Texas A&M University, College Station TX 77843.
Sunil P. Khatri , Department of ECE, Texas A&M University, College Station TX 77843.
pp. 76-81

A Reconfigurable CAM Architecture for Network Search Engines (Abstract)

Mehrdad Nourani , Center for Integrated Circuits & Systems, The University of Texas at Dallas, Richardson, TX 75083. nourani@utdallas.edu
Deepak S. Vijayasarathi , Center for Integrated Circuits & Systems, The University of Texas at Dallas, Richardson, TX 75083. dxv033000@utdallas.edu
Poras T. Balsara , Center for Integrated Circuits & Systems, The University of Texas at Dallas, Richardson, TX 75083. poras@utdallas.edu
pp. 82-87

Delay and Area Efficient First-level Cache Soft Error Detection and Correction (PDF)

Karl C. Mohr , Arizona State University Dept. of Electrical Engineering, Tempe, AZ USA. karl.mohr@asu.edu
Lawrence T. Clark , Arizona State University Dept. of Electrical Engineering, Tempe, AZ USA. lawrence.clark@asu.edu
pp. 88-92

Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD (PDF)

Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
pp. 93-100

Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy (PDF)

Dan Nicolaescu , School of Information and Computer Science, University of California, Irvine. Email: dann@ics.uci.edu
Babak Salamat , School of Information and Computer Science, University of California, Irvine. Email: bsalamat@ics.uci.edu
Alex Veidenbaum , School of Information and Computer Science, University of California, Irvine. Email: alexv@ics.uci.edu
Mateo Valero , Computer Architecture Department, Polytechnical University of Catalunia, Spain. Email: mateo@ac.upc.es
pp. 101-107

Customizable Fault Tolerant Caches for Embedded Processors (PDF)

Subramanian Ramaswamy , Center for Research on Embedded Systems and Technology, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332. ramaswamy@gatech.edu
Sudhakar Yalamanchili , Center for Research on Embedded Systems and Technology, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332. sudha@ece.gatech.edu
pp. 108-113

Reduce Register Files Leakage Through Discharging Cells (PDF)

Lingling Jin , Dept. of Computer Science, Univ. of California, Riverside, 92521. Email: ljin@cs.ucr.edu
Wei Wu , Dept. of Computer Science, Univ. of California, Riverside, 92521. Email: wwu@cs.ucr.edu
Jun Yang , Dept. of Computer Science, Univ. of California, Riverside, 92521. Email: junyang@cs.ucr.edu
Chuanjun Zhang , Dept. of Computer Science, and Electrical Engineering, Univ. of Missouri-Kansas City, 64110. Email: zhangchu@umkc.edu
Youtao Zhang , Dept. of Computer Science, Univ. of Pittsburgh, 15260. Email: zhangyt@cs.pitt.edu
pp. 114-119

Efficient Transient-Fault Tolerance for Multithreaded Processors Using Dual-Thread Execution (PDF)

Yi Ma , School of Electrical Engineering and Computer Science, University of Central Florida. yma@cs.ucf.edu
Huiyang Zhou , School of Electrical Engineering and Computer Science, University of Central Florida. zhou@cs.ucf.edu
pp. 120-126

Polaris: A System-Level Roadmap for On-Chip Interconnection Networks (PDF)

Vassos Soteriou , Department of Electrical Engineering, Princeton University, Princeton, NJ 08544. soteriou@princeton.edu
Noel Eisley , Department of Electrical Engineering, Princeton University, Princeton, NJ 08544. eisley@princeton.edu
Hangsheng Wang , Freescale Semiconductor, 7700 W Parmer LN, Austin, TX 78729. hangshen@freescale.com
Bin Li , Department of Electrical Engineering, Princeton University, Princeton, NJ 08544. binl@princeton.edu
Li-Shiuan Peh , Department of Electrical Engineering, Princeton University, Princeton, NJ 08544. peh@princeton.edu
pp. 134-141

A Performance and Power Analysis of WK-Recursive and Mesh Networks for Network-on-Chips (PDF)

D. Rahmati , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
A. E. Kiasari , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran; School of Computer Science, Institute for Studies in theoretical Physics and Mathematics (IPM), Tehran, Iran
S. Hessabi , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
H. Sarbazi-Azad , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran; School of Computer Science, Institute for Studies in theoretical Physics and Mathematics (IPM), Tehran, Iran
pp. 142-147

Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors (PDF)

Sean Leventhal , School of Electrical and Computer Engineering, University of Maryland at College Park. sleventh@glue.umd.edu
Manoj Franklin , School of Electrical and Computer Engineering, University of Maryland at College Park. manoj@glue.umd.edu
pp. 148-154

A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals (PDF)

Kimiyoshi Usami , Shibaura Institute of Technology, 3-7-5 Toyosu, Kohtoh-ku, Tokyo 135-8548, Japan. usami@sic.shibaura-it.ac.jp, m105021@sic.shibaura-it.ac.jp
Naoaki Ohkubo , Shibaura Institute of Technology, 3-7-5 Toyosu, Kohtoh-ku, Tokyo 135-8548, Japan. m105021@sic.shibaura-it.ac.jp
pp. 155-161

Design Methodology of Regular Logic Bricks for Robust Integrated Circuits (PDF)

Kim Yaw Tong , Carnegie Mellon University. ktong@ece.cmu.edu
Vyacheslav Rovner , Carnegie Mellon University. vrovner@ece.cmu.edu
Lawrence T. Pileggi , Carnegie Mellon University. pileggi@ece.cmu.edu
Veerbhan Kheterpal , Carnegie Mellon University; Fabbrix Inc. veerbhan@fabbrix.com
pp. 162-167

An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks (PDF)

Sanjay Pant , University of Michigan, Ann Arbor, MI
David Blaauw , University of Michigan, Ann Arbor, MI
pp. 168-173

Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles (PDF)

Zhiyi Yu , ECE Department, University of California, Davis
Bevan Baas , ECE Department, University of California, Davis
pp. 174-179

Scale in Chip Interconnect requires Network Technology (PDF)

Enno Wein , Arteris, The Network-on-Chip Company, 2033 Gateway Place, San Jose, CA 95110. Email: enno.wein@arteris.com
pp. 180-186

Interconnect Considerations For High Performance Network on Chip Designs (PDF)

Uri Cummings , Fulcrum Microsystems. uri@fulcrummicro.com
pp. 187

Clustering-Based Microcode Compression (PDF)

Edson Borin , Institute of Computing, University of Campinas - Campinas, SP - Brazil. Email: borin@ic.unicamp.br
Mauricio Breternitz , Programming System Lab, Intel Corporation - Santa Clara, CA - USA. Email: mauricio.breternitz.jr@intel.com
Youfeg Wu , Programming System Lab, Intel Corporation - Santa Clara, CA - USA. Email: youfeng.wu@intel.com
Guido Araujo , Institute of Computing, University of Campinas - Campinas, SP - Brazil. Email: guido@ic.unicamp.br
pp. 189-196

Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-based Scheduling (PDF)

Kuo-Su Hsiao , Department of Electrical Engineering, National Cheng Kung University, No.1, Ta-Hsueh Road, Tainan 701, Taiwan. newjimmy@ee.ncku.edu.tw
Chung-Ho Chen , Department of Electrical Engineering, National Cheng Kung University, No.1, Ta-Hsueh Road, Tainan 701, Taiwan. chchen@mail.ncku.edu.tw, newjimmy@ee.ncku.edu.tw
pp. 197-202

An Enhancement for a Scheduling Logic Pipelined over two Cycles (PDF)

Ruben Gran , Departamento de Arquitectura de Computadores. Universidad PolitÚcnica de Catalu˝a. rgran@ac.upc.edu
Enric Morancho , Departamento de Arquitectura de Computadores. Universidad PolitÚcnica de Catalu˝a. enricm@ac.upc.edu
Angel Olive , Departamento de Arquitectura de Computadores. Universidad PolitÚcnica de Catalu˝a. angel@ac.upc.edu
Jose M. Llaberia , Departamento de Arquitectura de Computadores. Universidad PolitÚcnica de Catalu˝a. llaberia@ac.upc.edu
pp. 203-209

Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates (PDF)

Saraju P. Mohanty , Dept. of Computer Science and Engineering, University of North Texas, P. O. Box 311366, Denton, TX 76203. Email: smohanty@cse.unt.edu
Elias Kougianos , Dept. of Engineering Technology, University of North Texas, P. O. Box 310679, Denton, TX 76203. Email: eliask@unt.edu
pp. 210-215

Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI (Abstract)

Kunhyuk Kang , Dept. of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA
Haldun Kufluoglu , Dept. of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA
Muhammad Ashraful Alam , Dept. of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA
Kaushik Roy , Dept. of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA
pp. 216-221

Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction (PDF)

Andrew B. Kahng , University of California San Diego, Computer Science and Engineering Department. abk@cs.ucsd.edu
Rasit Onur Topaloglu , University of California San Diego, Computer Science and Engineering Department. rtopalog@cs.ucsd.edu
pp. 222-229

Power-Constrained SOC Test Schedules through Utilization of Functional Buses (PDF)

Fawnizu Azmadi Hussin , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science City, 630-0192, Japan. fawniz-h@is.naist.jp
Tomokazu Yoneda , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science City, 630-0192, Japan. yoneda@is.naist.jp
Hideo Fujiwara , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science City, 630-0192, Japan. fujiwara@is.naist.jp
Alex Orailoglu , Computer Science and Engineering Department, University of California San Diego, La Jolla, CA 92093. alex@cs.ucsd.edu
pp. 230-236

RTL Scan Design for Skewed-Load At-Speed Test under Power Constraints (PDF)

Ho Fai Ko , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, L8S 4K1, Canada. Email: henryko@grads.ece.mcmaster.ca
Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, L8S 4K1, Canada. Email: nicola@ece.mcmaster.ca
pp. 237-242

Power Droop Testing (PDF)

Ilia Polian , Albert-Ludwigs-University, Georges-K÷ler-Allee 51, 79110 Freiburg, Germany. polian@informatik.uni-freiburg.de
Alejandro Czutro , Albert-Ludwigs-University, Georges-K÷ler-Allee 51, 79110 Freiburg, Germany. aczutro@informatik.uni-freiburg.de
Sandip Kundu , Department of ECE, University of Massachusetts, Amherst, MA 01003, USA. kundu@ecs.umass.edu
Bernd Becker , Albert-Ludwigs-University, Georges-K÷ler-Allee 51, 79110 Freiburg, Germany. becker@informatik.uni-freiburg.de
pp. 243-250

A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation (PDF)

Xiaoqing Wen , Dept. of CSE, Kyushu Institute of Technology, Iizuka, 820-8502, Japan. phone: +81-948-29-7891; fax: +81-948-29-7651; e-mail: wen@cse.kyutech.ac.jp
Kohei Miyase , Innovation Plaza Fukuoka, JST, Fukuoka 814-0001, Japan. e-mail: miyase@fukuoka.jst-plaza.jp
Tatsuya Suzuki , Dept. of CSE, Kyushu Institute of Technology, Iizuka 820-8502, Japan. e-mail: suzuki@aries30.cse.kyutech.ac.jp
Yuta Yamato , Dept. of CSE, Kyushu Institute of Technology, Iizuka 820-8502, Japan. e-mail: yamato@aries30.cse.kyutech.ac.jp
Seiji Kajihara , Dept. of CSE, Kyushu Institute of Technology, Iizuka 820-8502, Japan. e-mail: kajihara@cse.kyutech.ac.jp
Laung-Terng Wang , SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, Sunnyvale, CA 94086, USA. e-mail: wang@syntest.com
Kewal K. Saluja , Dept. of ECE, 1415 Engineering Drive, University of Wisconsin - Madison, Madison, WI 53706, USA. e-mail: saluja@ece.wisc.edu
pp. 251-258

Scalable Sequential Equivalence Checking across Arbitrary Design Transformations (PDF)

Jason Baumgartner , IBM Systems & Technology Group
Hari Mony , IBM Systems & Technology Group
Viresh Paruthi , IBM Systems & Technology Group
Robert Kanzelman , IBM Systems & Technology Group
Geert Janssen , IBM Research Division
pp. 259-266

Seqver : A Sequential Equivalence Verifier for Hardware Designs (PDF)

Daher Kaiss , Formal Technologies Group, Intel Corporation. daher.kaiss@intel.com
Silvian Goldenberg , Digital Enterprise Group, Intel Corporation. silvian.goldenberg@intel.com
Ziyad Hanna , Formal Technologies Group, Intel Corporation. ziyad.hanna@intel.com
Zurab Khasidashvili , Formal Technologies Group, Intel Corporation. zurab.khasidashvili@intel.com
pp. 267-273

High-Level vs. RTL Combinational Equivalence: An Introduction (PDF)

Alan J. Hu , Department of Computer Science, University of British Columbia. ajh@cs.ubc.ca
pp. 274-279

Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation Technique (PDF)

Kameshwar Chandrasekar , Intel Corporation, Santa Clara, CA 95054. Email: kameshwar.chandrasekar@intel.com
Michael S. Hsiao , Virginia Tech, Blacksburg, VA 24061. Email: mhsiao@vt.edu
pp. 280-285

Requirements and Concepts for Transaction Level Assertions (PDF)

Wolfgang Ecker , Infineon Technologies AG, Munich, Germany. Email: Wolfgang.Ecker@infineon.com
Volkan Esen , Infineon Technologies AG, TU Darmstadt - MES. Email: Volkan.Esen@infineon.com
Thomas Steininger , Infineon Technologies AG, TU Darmstadt - MES. Email: Thomas.Steininger@infineon.com
Michael Velten , Infineon Technologies AG, TU Darmstadt - MES. Email: Michael.Velten@infineon.com
Michael Hull , Infineon Technologies AG, University of Southampton. Email: mh102@ecs.soton.ac.uk
pp. 286-293

Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug (PDF)

Marc Boule , McGill University, marc.boule@elf.mcgill.ca
Jean-Samuel Chenard , McGill University, jsamch@macs.ece.mcgill.ca
Zeljko Zilic , McGill University, zeljko@macs.ece.mcgill.ca
pp. 294-299

Simulation-based functional test justification using a Boolean data miner (PDF)

Charles H.-P. Wen , Dept. of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106. Email: opwen@ece.ucsb.edu
Onur Guzey , Dept. of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106. Email: oguzey@ece.ucsb.edu
Li-C. Wang , Dept. of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106. Email: licwang@ece.ucsb.edu
Jin Yang , Strategic CAD Lab, Intel Corporation. Email: jin.yang@intel.com
pp. 300-307

FPGA Implementation of High Speed FIR Filters Using Add and Shift Method (PDF)

Shahnam Mirzaei , University Of California, Santa Barbara, CA 93106. E-mail: shahnam@umail.ucsb.edu
Anup Hosangadi , University Of California, Santa Barbara, CA 93106. E-mail: anup@ece.ucsb.edu
Ryan Kastner , University Of California, Santa Barbara, CA 93106. E-mail: kastner@ece.ucsb.edu
pp. 308-313

FPGA-based Design of a Large Moduli Multiplier for Public-Key Cryptographic Systems (PDF)

Osama Al-Khaleel , Case Western Reserve University, Cleveland, Ohio 44106, USA. oda@case.edu
Chris Papachristou , Case Western Reserve University, Cleveland, Ohio 44106, USA. oda@case.edu, cap2@case.edu
Francis Wolff , Case Western Reserve University, Cleveland, Ohio 44106, USA. oda@case.edu, fxw12@case.edu
Kiamal Pekmestzi , National Technical University, 157 80 Athens - Greece. pekmes@microlab.ntua.gr
pp. 314-319

Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture (Abstract)

T. Mohsenin , ECE Department, University of California, Davis
B. M. Baas , ECE Department, University of California, Davis
pp. 320-325

An Efficient, Scalable Hardware Engine for Boolean SATisfiability (PDF)

Mandar Waghmode , Magma Design Automation, Inc. Santa Clara, CA 95054.
Kanupriya Gulati , Department of EE, Texas A&M University, College Station TX 77843.
Sunil P Khatri , Department of EE, Texas A&M University, College Station TX 77843.
Weiping Shi , Department of EE, Texas A&M University, College Station TX 77843.
pp. 326-331

Power/Ground Supply Network Optimization for Power-Gating (PDF)

Hailin Jiang , ECE Department, UCSB. hailin@ece.ucsb.edu
Malgorzata Marek-Sadowska , ECE Department, UCSB. mms@ece.ucsb.edu
pp. 332-337

A Pattern Generation Technique for Maximizing Power Supply Currents (PDF)

Kunal Ganeshpure , Electrical and Computer Engineering, University of Massachusetts, Amherst. kganeshp@ecs.umass.edu
Alodeep Sanyal , Electrical and Computer Engineering, University of Massachusetts, Amherst. asanyal@ecs.umass.edu
Sandip Kundu , Electrical and Computer Engineering, University of Massachusetts, Amherst. kundu@ecs.umass.edu
pp. 338-343

Partial Functional Manipulation Based Wirelength Minimization (PDF)

Avijit Dutta , Comp Engineering Research Center, University of Texas at Austin
David Z. Pan , Comp Engineering Research Center, University of Texas at Austin
pp. 344-349

Iterative-Constructive Standard Cell Placer for High Speed and Low Power (PDF)

Sungjae Kim , Department of Computer Science and Engineering, University of Minnesota, Minneapolis, MN 55455. Email: sukim@cs.umn.edu
Eugene Shragowitz , Department of Computer Science and Engineering, University of Minnesota, Minneapolis, MN 55455. Email: shragowi@cs.umn.edu
pp. 350-355

Generic Architecture Description for Retargetable Compilation and Synthesis of Application-Specific Pipelined IPs (PDF)

Bita Gorjiara , Center for Embedded Computer Systems, University of California, Irvine. bgorjiar@cecs.uci.edu
Mehrdad Reshadi , Center for Embedded Computer Systems, University of California, Irvine. reshadi@cecs.uci.edu
Daniel Gajski , Center for Embedded Computer Systems, University of California, Irvine. gajski@cecs.uci.edu
pp. 356-361

Assertion-Based Microarchitecture Design for Improved Fault Tolerance (PDF)

Vimal K. Reddy , Department of Electrical and Computer Engineering, North Carolina State University, vkreddy@ece.ncsu.edu
Ahmed S. Al-Zawawi , Department of Electrical and Computer Engineering, North Carolina State University, aalzawa@ece.ncsu.edu
Eric Rotenberg , Department of Electrical and Computer Engineering, North Carolina State University, ericro@ece.ncsu.edu
pp. 362-369

High-Speed Factorization Architecture for Soft-Decision Reed-Solomon Decoding (PDF)

Xinmiao Zhang , Department of Electrical Engineering and Computer Science, Case Western Reserve University, 10900 Euclid Ave., Cleveland, OH 44106-7071
pp. 370-375

Guiding Architectural SRAM Models (PDF)

Banit Agrawal , Department of Computer Science, University of California, Santa Barbara. Email: banit@cs.ucsb.edu
Timothy Sherwood , Department of Computer Science, University of California, Santa Barbara. Email: sherwood@cs.ucsb.edu
pp. 376-382

A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models (PDF)

Jinwen Xi , Dept. of Electrical and Computer Engineering, Michigan State Univeristy, East Lansing, MI 48824, U.S.A. xijinwen@egr.msu.edu
Peixin Zhong , Member, IEEE, Dept. of Electrical and Computer Engineering, Michigan State Univeristy, East Lansing, MI 48824, U.S.A. pzhong@egr.msu.edu
pp. 383-388

Reliability Support for On-Chip Memories Using Networks-on-Chip (PDF)

Federico Angiolini , DEIS, University of Bologna, Bologna, Italy.
David Atienza , LSI/EPFL, Lausanne, Switzerland; DACYA/UCM, Madrid, Spain.
Srinivasan Murali , LSI/EPFL, Lausanne, Switzerland; Stanford University, Palo Alto, USA.
Luca Benini , DEIS, University of Bologna, Bologna, Italy.
Giovanni De Micheli , LSI/EPFL, Lausanne, Switzerland.
pp. 389-396

Task Merging for Dynamic Power Management of Cyclic Applications in Real-Time Multiprocessor Systems (PDF)

Qinru Qiu , Department of Electrical and Computer Engineering, Binghamton University, State University of New York, Binghamton, NY 13902 USA. qqiu@binghamton.edu
Shaobo Liu , Department of Electrical and Computer Engineering, Binghamton University, State University of New York, Binghamton, NY 13902 USA. sliu5@binghamton.edu
Qing Wu , Department of Electrical and Computer Engineering, Binghamton University, State University of New York, Binghamton, NY 13902 USA. qwu@binghamton.edu
pp. 397-404

A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems (PDF)

Chuanjun Zhang , Department of Computer Science and Electrical Engineering, University of Missouri-Kansas City. zhangchu@umkc.edu
pp. 405-410

System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors (Abstract)

Xiaofang Wang , Dept. of Electrical and Computer Engineering, Villanova University, Villanova, PA 19085. xiaofang.wang@villanova.edu
Sotirios G. Ziavras , Dept. of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ 07102. ziavras@njit.edu
Jie Hu , Dept. of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ 07102. jhu@njit.edu
pp. 411-416

Improving Power and Data Efficiency with Threaded Memory Modules (PDF)

Frederick A. Ware , Rambus Inc., Los Altos CA, 94022. ware@Rambus.com
Craig Hampel , Member, IEEE, Rambus Inc., Los Altos CA, 94022. champel@Rambus.com
pp. 417-424

A New Class of Sequential Circuits with Acyclic Test Generation Complexity (PDF)

Chia Yee Ooi , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science City, 630-0192 Nara, Japan. chiaye-o@is.naist.jp
Hideo Fujiwara , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science City, 630-0192 Nara, Japan. fujiwara@is.naist.jp
pp. 425-431

Efficient Testing of RF MIMO Transceivers Used in WLAN Applications (PDF)

Erkan Acar , Duke University, Durham, NC. ea5@ee.duke.edu
Sule Ozev , Duke University, Durham, NC. sule@ee.duke.edu
pp. 432-437

A Theory of Error-Rate Testing (PDF)

Shideh Shahidi , Electrical Engineering Department, University of Southern California, Los Angeles, CA 90089. sshahidi@poisson.usc.edu
Sandeep K. Gupta , Electrical Engineering Department, University of Southern California, Los Angeles, CA 90089. sandeep@poisson.usc.edu
pp. 438-445

Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests (PDF)

Dong Xiang , School of Software, Tsinghua University, Beijing 100084, China. dxiang@tsinghua.edu.cn
Kaiwei Li , School of Software, Tsinghua University, Beijing 100084. likaiwei@mails.tsinghua.edu.cn
Hideo Fujiwara , Grad. Sch. of Inform. Sci., Nara Institute of Sci. and Techn., Ikoma, Nara 630-0101, Japan. fujiwara@is.naist.jp
Jiaguang Sun , School of Software, Tsinghua University, Beijing 100084. sunjg@tsinghua.edu.cn
pp. 446-451

Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach (PDF)

Hwisung Jung , Department of Electrical Engineering, University of Southern California. hwijung@usc.edu
Massoud Pedram , Department of Electrical Engineering, University of Southern California. pedram@usc.edu
pp. 452-457

Design and Implementation of Software Objects in Hardware (PDF)

Fu-Chiung Cheng , Department of Computer Science and Engineering, Tatung University, Taipei, 104 Taiwan, R.O.C. fccheng@ttu.edu.tw
Hung-Chi Wu , Department of Computer Science and Engineering, Tatung University, Taipei, 104 Taiwan, R.O.C. wuandy@ms10.hinet.net
pp. 458-463

An Accurate Energy Estimation Framework for VLIW Processor Cores (PDF)

Sourav Roy , India Design Center, Freescale Semiconductors. sourav.roy@freescale.com
Rajat Bhatia , India Design Center, Freescale Semiconductors. rajat.bhatia@freescale.com
Ashish Mathur , India Design Center, Freescale Semiconductors. ashish.mathur@freescale.com
pp. 464-469

Design and Implementation of the TRIPS Primary Memory System (PDF)

Simha Sethumadhavan , Computer Architecture and Technology Laboratory, Department of Computer Sciences, The University of Texas at Austin. cart@cs.utexas.edu
Robert McDonald , Computer Architecture and Technology Laboratory, Department of Computer Sciences, The University of Texas at Austin. cart@cs.utexas.edu
Rajagopalan Desikan , Computer Architecture and Technology Laboratory, Department of Electrical and Computer Engineering, The University of Texas at Austin. cart@cs.utexas.edu
Doug Burger , Computer Architecture and Technology Laboratory, Department of Computer Sciences, The University of Texas at Austin. cart@cs.utexas.edu
Stephen W. Keckler , Computer Architecture and Technology Laboratory, Department of Computer Sciences, The University of Texas at Austin. cart@cs.utexas.edu
pp. 470-476

Implementation and Evaluation of On-Chip Network Architectures (PDF)

Paul Gratz , Department of Electrical and Computer Engineering, University of Texas at Austin. pgratz@cs.utexas.edu
Changkyu Kim , Department of Computer Sciences, University of Texas at Austin. ckkim@cs.utexas.edu
Robert McDonald , Department of Computer Sciences, University of Texas at Austin. robertmc@cs.utexas.edu
Stephen W. Keckler , Department of Computer Sciences, University of Texas at Austin. skeckler@cs.utexas.edu
Doug Burger , Department of Computer Sciences, University of Texas at Austin. dburger@cs.utexas.edu
pp. 477-484

Microarchitecture and Performance Analysis of Godson-2 SMT Processor (PDF)

Zusong Li , Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100080. lisoon@ict.ac.cn
Xianchao Xu , Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100080. xuxianchao@ict.ac.cn
Weiwu Hu , Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100080. hww@ict.ac.cn
Zhimin Tang , Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100080. tang@ict.ac.cn
pp. 485-490

Patching Processor Design Errors (PDF)

Satish Narayanasamy , Department of Computer Science and Engineering, University of California, San Diego. satish@cs.ucsd.edu
Bruce Carneal , Department of Computer Science and Engineering, University of California, San Diego. bcarneal@cs.ucsd.edu
Brad Calder , Department of Computer Science and Engineering, University of California, San Diego. calder@cs.ucsd.edu
pp. 491-498

Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache (PDF)

Nathan N. Sadler , Department of Electrical and Computer Engineering, Duke University. nns@ee.duke.edu
Daniel J. Sorin , Department of Electrical and Computer Engineering, Duke University. sorin@ee.duke.edu
pp. 499-505

Architectural Support for Run-Time Validation of Control Flow Transfer (PDF)

Yixin Shi , Department of Electrical and Computer Engineering, University of Illinois at Chicago, Chicago, IL 60607. yshi7@uic.edu
Sean Dempsey , Department of Electrical and Computer Engineering, University of Illinois at Chicago, Chicago, IL 60607. sdemp1@uic.edu
Gyungho Lee , Department of Electrical and Computer Engineering, University of Illinois at Chicago, Chicago, IL 60607. ghlee@ece.uic.edu
pp. 506-513

Pesticide: Using SMT to Improve Performance of Pointer-Bug Detection (PDF)

Jin-Yi Wang , School of Electrical and Computer Engineering, Purdue University. jywang@ecn.purdue.edu
Yen-Shiang Shue , School of Electrical and Computer Engineering, Purdue University. shue@ecn.purdue.edu
T. N. Vijaykumar , School of Electrical and Computer Engineering, Purdue University. vijay@ecn.purdue.edu
Saurabh Bagchi , School of Electrical and Computer Engineering, Purdue University. sbagchi@ecn.purdue.edu
pp. 514-521

Trends and Future Directions in Nano Structure Based Computing and Fabrication (PDF)

R. Iris Bahar , Division of Engineering, Brown University, Providence, RI 02912. Email: iris_bahar@brown.edu
pp. 522-527
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