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Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93 (1993)
Cambridge, MA, USA
Oct. 3, 1993 to Oct. 6, 1993
ISBN: 0-8186-4230-0
TABLE OF CONTENTS

A new modulo 2/sup a/+1 multiplier (PDF)

A. Wrzyszcz , Dept. of Electr. & Electron. Eng., Bristol Univ., UK
D. Milford , Dept. of Electr. & Electron. Eng., Bristol Univ., UK
pp. 614-617

Concurrent error detection in nonlinear digital circuits with applications to adaptive filters (PDF)

A. Chatterjee , Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 606-609

Fast CRC calculation (PDF)

R.J. Glaise , IBM CER LaGaude, France
X. Jacquart , IBM CER LaGaude, France
pp. 602-605

Quiescent current monitoring to improve the reliability of electronic systems in space radiation environments (PDF)

F. Vargas , TIMA/INPG Lab., Grenoble, France
M. Nicolaidis , TIMA/INPG Lab., Grenoble, France
B. Courtois , TIMA/INPG Lab., Grenoble, France
pp. 596-600

Efficient diagnosis in algorithm-based fault tolerant multiprocessor systems (PDF)

S. Srinivasan , Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 592-595

/spl Phi/-test: Perfect hashed index test for test response validation (PDF)

R. Gupta , General Electric Corp. R&D, Schenectady, NY, USA
pp. 588-591

Influence of error correlations on the signature analysis aliasing (PDF)

R. Leveugle , Inst. Nat. Polytech. de Grenoble/CSI, France
X. Delord , Inst. Nat. Polytech. de Grenoble/CSI, France
G. Saucier , Inst. Nat. Polytech. de Grenoble/CSI, France
pp. 584-587

An adaptive technique for dynamic rollback in concurrent event-driven fault simulation (PDF)

L. Farinetti , Dip. di Autom. e Inf., Politecnico di Torino, Italy
P.L. Montessoro , Dip. di Autom. e Inf., Politecnico di Torino, Italy
pp. 576-582

Functional fault models and gate level coverage for sequential architectures (PDF)

G. Buonanno , Dipartimento di Elettronica, Politecnico di Milano, Italy
F. Fummi , Dipartimento di Elettronica, Politecnico di Milano, Italy
D. Sciuto , Dipartimento di Elettronica, Politecnico di Milano, Italy
pp. 572-575

MIXER: Mixed-signal fault simulator (PDF)

N. Nagi , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 568-571

Newton: Performance improvement through comparative analysis (PDF)

L.D. Kipp , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
D. Kuck , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
pp. 558-561

System-level specification of instruction sets (PDF)

T.A. Cook , North Carolina State Univ., Raleigh, NC, USA
P.D. Franzon , North Carolina State Univ., Raleigh, NC, USA
E.A. Harcourt , North Carolina State Univ., Raleigh, NC, USA
T.K. Miller , North Carolina State Univ., Raleigh, NC, USA
pp. 552-557

A framework for specifying and designing pipelines (PDF)

M. Aagaard , Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
M. Leeser , Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
pp. 548-551

Complex gate performance improvement by jog insertion into transistor gates (PDF)

R.D. Hindmarsh , Inst. fur Tech. Inf., Tech. Univ. Berlin, Germany
pp. 543-546

A logic-level model for /spl alpha/-particle hits in CMOS circuits (PDF)

H. Cha , Center for Reliable & High-Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel , Center for Reliable & High-Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 538-542

Computer-aided redesign of VLSI circuits for hot-carrier reliability (PDF)

P.-C. Li , ECE Dept., Illinois Univ., Urbana, IL, USA
I.N. Hajj , ECE Dept., Illinois Univ., Urbana, IL, USA
pp. 534-537

Test path generation and test scheduling for self-testable designs (PDF)

A. Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
I.G. Harris , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 528-531

Pseudoexhaustive BIST for sequential circuits (PDF)

D. Kagaris , Comput. Sci. Program, Dartmouth Coll., Hanover, NH, USA
pp. 523-527

Design for testability of asynchronous sequential circuits (PDF)

J. Saxena , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
D.K. Pradhan , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 518-522

Efficient symbolic support manipulation (PDF)

B. Lin , IMEC Lab., Leuven, Belgium
pp. 513-516

Some results on the complexity of Boolean functions for table look up architectures (PDF)

R. Murgai , Dept. of EECS, California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of EECS, California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of EECS, California Univ., Berkeley, CA, USA
pp. 505-512

A field programmable accelerator for compiled-code applications (PDF)

D.M. Lewis , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
M.H. van Ierssel , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
D.H. Wong , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 491-496

Beyond superscalar using FPGAs (PDF)

C. Iseli , Logic Syst. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland
E. Sanchez , Logic Syst. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland
pp. 486-490

The Splash 2 processor and applications (PDF)

J.M. Arnold , IDA Supercomput. Res. Center, Bowie, MD, USA
D.A. Buell , IDA Supercomput. Res. Center, Bowie, MD, USA
D.T. Hoang , IDA Supercomput. Res. Center, Bowie, MD, USA
D.V. Pryor , IDA Supercomput. Res. Center, Bowie, MD, USA
N. Shirazi , IDA Supercomput. Res. Center, Bowie, MD, USA
M.R. Thistle , IDA Supercomput. Res. Center, Bowie, MD, USA
pp. 482-485

Neighbour state transition method for VLSI optimization problems (PDF)

D. Zhou , EE Dept., Univ. of North Carolina, Charlotte, NC, USA
pp. 476-479

An exact rectilinear Steiner tree algorithm (PDF)

J.S. Salowe , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
D.M. Warme , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 472-475

Strongly NP-hard discrete gate sizing problems (PDF)

W.N. Li , Dept. of Comput. Sci., Arkansas Univ., Fayetteville, AR, USA
pp. 468-471

Partitioning and surmounting the software-hardware abstraction gap in an ASIC design project (PDF)

K. ten Hagen , Aachen Univ. of Technol., Germany
H. Meyr , Aachen Univ. of Technol., Germany
pp. 462-465

System factorization in codesign. A case study of the use of formal techniques to achieve hardware-software decomposition (PDF)

B. Bose , Dept. of Comput. Sci. Indiana Univ., Bloomington, IN, USA
M.E. Tuna , Dept. of Comput. Sci. Indiana Univ., Bloomington, IN, USA
S.D. Johnson , Dept. of Comput. Sci. Indiana Univ., Bloomington, IN, USA
pp. 458-461

Fast timing analysis for hardware-software co-synthesis (PDF)

W. Ye , Inst. fur Datenverabeitungsanlagen, Tech. Univ. Braunschweig, Germany
R. Ernst , Inst. fur Datenverabeitungsanlagen, Tech. Univ. Braunschweig, Germany
T. Benner , Inst. fur Datenverabeitungsanlagen, Tech. Univ. Braunschweig, Germany
pp. 452-457

Formal semantics of VHDL for verification of circuit designs (PDF)

G.X. Hua , Dept. of Comput. Sci., Iowa Univ., IA, USA
H. Zhang , Dept. of Comput. Sci., Iowa Univ., IA, USA
pp. 446-449

Physically realizable gate models (PDF)

P.R. Stephan , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 442-445

Derivation of a DRAM memory interface by sequential decomposition (PDF)

K. Rath , Dept. of Comput. Sci., Indiana Univ., Bloomington, IN, USA
B. Bose , Dept. of Comput. Sci., Indiana Univ., Bloomington, IN, USA
S.D. Johnson , Dept. of Comput. Sci., Indiana Univ., Bloomington, IN, USA
pp. 438-441

Heuristic minimization of synchronous relations (PDF)

V. Singhal , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Y. Watanabe , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 428-433

Logic optimization with multi-output gates (PDF)

Y. Watanabe , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
L. Guerra , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 416-420

Pica: An ultra-light processor for high-throughput applications (PDF)

D.S. Wills , Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
W.S. Lacy , Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
H. Cat , Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 410-414

A systolic architecture for high speed pipelined memories (PDF)

A.G. Dickinson , AT&T Bell Lab., Holmdel, NJ, USA
C.J. Nicol , AT&T Bell Lab., Holmdel, NJ, USA
pp. 406-409

A systolic array for approximate string matching (PDF)

R. Sastry , Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL, USA
N. Ranganathan , Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL, USA
pp. 402-405

Design guidelines and testability assessment (PDF)

B.R. Wilkins , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
C. Shi , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
pp. 388-391

Economics in design and test (PDF)

C. Dislis , Brunel Univ., Uxbridge, UK
A.P. Ambler , Brunel Univ., Uxbridge, UK
I.D. Dear , Brunel Univ., Uxbridge, UK
pp. 384-387

Library-adaptively integrated data path synthesis for DSP systems (PDF)

J.-M. Jou , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
S.-R. Kuang , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 379-382

Cluster-oriented scheduling in pipelined data path synthesis (PDF)

C.-T. Chang , Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
K. Rose , Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
R.A. Walker , Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
pp. 374-378

Global mobility based scheduling (PDF)

U. Prabhu , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
B.M. Pangrle , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 370-373

Optimal scheduling of finite-state machines (PDF)

T.-Y. Yen , Dept. of Electr. Eng., Princeton Univ., NJ, USA
W. Wolf , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 366-369

Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation (PDF)

M.A. Riepe , Michigan Univ., MI, USA
J.P. Marques Silva , Michigan Univ., MI, USA
K.A. Sakallah , Michigan Univ., MI, USA
R.B. Brown , Michigan Univ., MI, USA
pp. 361-364

ACES: a transient simulation strategy for integrated circuits (PDF)

A. Devgan , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.A. Rohrer , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 357-360

Analysis and control of timing jitter in digital logic arising from noise voltage sources (PDF)

P.-S. Lin , Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
C.A. Zukowski , Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
pp. 352-356

Multiple-page translation for TLB (PDF)

L. Liu , IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 344-349

Trail: a track-based logging disk architecture for zero-overhead writes (PDF)

T.-C. Chiueh , Dept. of Comput. Sci. State Univ. of New York, Stony Brook, NY, USA
pp. 339-343

A memory controller with an integrated graphics processor (PDF)

J. Watkins , Sun Microsystems, Inc., Mountain View, CA, USA
R. Roth , Sun Microsystems, Inc., Mountain View, CA, USA
M. Hsieh , Sun Microsystems, Inc., Mountain View, CA, USA
W. Radke , Sun Microsystems, Inc., Mountain View, CA, USA
D. Hejna , Sun Microsystems, Inc., Mountain View, CA, USA
B. Kim , Sun Microsystems, Inc., Mountain View, CA, USA
pp. 324-338

A comparative evaluation of adders based on performance and testability (PDF)

R. Jayabharathi , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
T. Thomas , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 314-317

Reducing the cost of test pattern generation by information reusing (PDF)

W. Li , Dept. of Comput. Sci., Saskatchewan Univ., Saskatoon, Sask., Canada
C. McCrosky , Dept. of Comput. Sci., Saskatchewan Univ., Saskatoon, Sask., Canada
M. Abd-El-Barr , Dept. of Comput. Sci., Saskatchewan Univ., Saskatoon, Sask., Canada
pp. 310-313

Exploiting cofactoring for efficient FSM symbolic traversal based on the transition relation (PDF)

G. Cabodi , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Camurati , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 299-303

An efficient symbolic design verification system (PDF)

J. Park , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M.R. Mercer , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 294-298

A novel clock distribution system for CMOS VLSI (PDF)

K. Ishibashi , Hitachi Ltd., Tokyo, Japan
T. Hayashi , Hitachi Ltd., Tokyo, Japan
T. Doi , Hitachi Ltd., Tokyo, Japan
N. Masuda , Hitachi Ltd., Tokyo, Japan
pp. 289-292

A vector memory system based on wafer-scale integrated memory arrays (PDF)

T.-C. Chiueh , Dept. of Comput. Sci., State Univ. of New York, Stony Brook, NY, USA
pp. 284-288

A three-dimensional mesh multiprocessor system using board-to-board free-space optical interconnects: COSINE-III (PDF)

T. Sakano , NTT Transmission Syst. Lab., Kanagawa, Japan
T. Matsumoto , NTT Transmission Syst. Lab., Kanagawa, Japan
K. Noguchi , NTT Transmission Syst. Lab., Kanagawa, Japan
pp. 278-283

Hybrid number representations with bounded carry propagation chains (PDF)

D.S. Phatak , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
I. Koren , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
H. Choi , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 272-275

A note about the correction cycle of high radix Booth's multiplication (PDF)

G. Guo , EE & CS Dept., Texas A&I Univ., Kingsville, TX, USA
M. Ashtijou , EE & CS Dept., Texas A&I Univ., Kingsville, TX, USA
pp. 268-271

Design of the Intel Pentium processor (PDF)

A. Saini , Intel Corp., Santa Clara, CA, USA
pp. 258-261

The PowerPC 601 design methodology (PDF)

T. Brodnax , IBM Corp., Austin, TX, USA
M. Schiffli , IBM Corp., Austin, TX, USA
F. Watson , IBM Corp., Austin, TX, USA
pp. 248-252

Specification and synthesis of a mixed-mode systems: Experiments in a VHDL environment (PDF)

P.A. Subrahmanyam , AT&T Bell Lab., Holmdel, NJ, USA
J.M. Espinalt , AT&T Bell Lab., Holmdel, NJ, USA
M.-L. Yu , AT&T Bell Lab., Holmdel, NJ, USA
pp. 235-241

Efficient verification of symmetric concurrent systems (PDF)

C.N. Ip , Dept. of Comput. Sci., Stanford Univ., CA, USA
D.L. Dill , Dept. of Comput. Sci., Stanford Univ., CA, USA
pp. 230-234

A reconfiguration-based yield enhancement system (PDF)

J. Narasimhan , IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 224-228

A new high performance field programmable gate array family (PDF)

T. Whitney , Actel Corp., Sunnyvale, CA, USA
J. Schlageter , Actel Corp., Sunnyvale, CA, USA
pp. 216-219

A 8.8-ns 54/spl times/54-bit multiplier using new redundant binary architecture (PDF)

H. Makino , Mitsubishi Electr. Corp., Mizuhara, Itami, Japan
Y. Nakase , Mitsubishi Electr. Corp., Mizuhara, Itami, Japan
H. Shinohara , Mitsubishi Electr. Corp., Mizuhara, Itami, Japan
pp. 202-205

A 400 MHz wave-pipelined 8/spl times/8-bit multiplier in CMOS technology (PDF)

D. Ghosh , Texas Instrum. Pvt. Ltd., Bangalore, India
pp. 198-201

Fault-tolerant content addressable memory (PDF)

J.-C. Lo , Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA
pp. 193-196

Hardware self-tuning and circuit performance monitoring (PDF)

T. Kehl , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 188-192

SMAC: A scene matching chip (PDF)

N. Ranganathan , Center for Microelectron. Res., South Florida Univ., Tampa, FL, USA
R. Sastry , Center for Microelectron. Res., South Florida Univ., Tampa, FL, USA
R. Venkatesan , Center for Microelectron. Res., South Florida Univ., Tampa, FL, USA
J.W. Yoder , Center for Microelectron. Res., South Florida Univ., Tampa, FL, USA
D. Keezer , Center for Microelectron. Res., South Florida Univ., Tampa, FL, USA
pp. 184-187

A comparison of synchronous and asynchronous FSMD designs (PDF)

R. Auletta , Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA
pp. 178-182

An efficient unique state coding algorithm for signal transition graphs (PDF)

E. Pastor , Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Barcelona, Spain
J. Cortadella , Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 174-177

An algorithm for exact bounds on the time separation of events in concurrent systems (PDF)

T. Amon , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
H. Hulgaard , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
S.M. Burns , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
G. Borriello , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 166-173

ASLCScan: A scan design technique for asynchronous sequential logic circuits (PDF)

C.-L. Wey , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
M.-D. Shieh , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
P.D. Fisher , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
pp. 159-162

Bit-splitting for testability enhancement in scan-based design (PDF)

X. Xie , Dept. of Electr. Eng., Rochester Univ., NY, USA
A. Albicki , Dept. of Electr. Eng., Rochester Univ., NY, USA
pp. 155-158

Synthesis of sequential circuits for easy testability through performance-oriented parallel partial scan (PDF)

S. Bhatia , Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 151-154

A partial scan cost estimation method at the system level (PDF)

S. Chiu , Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
C.A. Papachristou , Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
pp. 146-150

The spring scheduling co-processor: a scheduling accelerator (PDF)

W. Burleson , Massachusetts Univ., Amherst, MA, USA
J. Ko , Massachusetts Univ., Amherst, MA, USA
D. Niehaus , Massachusetts Univ., Amherst, MA, USA
K. Ramamritham , Massachusetts Univ., Amherst, MA, USA
J.A. Stankovic , Massachusetts Univ., Amherst, MA, USA
G. Wallace , Massachusetts Univ., Amherst, MA, USA
C. Weems , Massachusetts Univ., Amherst, MA, USA
pp. 140-144

Evaluation of an object-caching coprocessor design for object-oriented systems (PDF)

J.M. Chang , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
E.F. Gehringer , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 132-139

Speculative computation for coprocessor synthesis (PDF)

U. Holtmann , Tech. Univ. Braunschweig, Germany
R. Ernst , Tech. Univ. Braunschweig, Germany
pp. 126-131

An integrated environment for concurrent development of a pixel processor ASIC and application software (PDF)

R. Roth , Sun Microsyst. Comput. Corp., Mountain View, CA, USA
J. Watkins , Sun Microsyst. Comput. Corp., Mountain View, CA, USA
M. Hsieh , Sun Microsyst. Comput. Corp., Mountain View, CA, USA
W. Radke , Sun Microsyst. Comput. Corp., Mountain View, CA, USA
D. Hejna , Sun Microsyst. Comput. Corp., Mountain View, CA, USA
R. Tom , Sun Microsyst. Comput. Corp., Mountain View, CA, USA
B. Kim , Sun Microsyst. Comput. Corp., Mountain View, CA, USA
pp. 116-125

Speculative execution and reducing branch penalty in a parallel issue machine (PDF)

H. Ando , Mitsubishi Electric Corp, Japan
C. Nakanishi , Mitsubishi Electric Corp, Japan
H. Machida , Mitsubishi Electric Corp, Japan
T. Hara , Mitsubishi Electric Corp, Japan
pp. 106-113

Area and performance comparison of pipelined RISC processors implementing different precise interrupt methods (PDF)

C.-J. Wang , Dept. of Electr. & Comput. Eng., Colorado Univ., Colorado Springs, CO, USA
pp. 102-105

Determining cost-effective multiple issue processor designs (PDF)

T.M. Conte , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
pp. 94-101

Architecture-compatible code boosting for performance enhancement of the IBM RS/6000 (PDF)

T.A. Diep , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
M.H. Lipasti , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.P. Shen , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 86-93

Fidelity and near-optimality of Elmore-based routing constructions (PDF)

K.D. Boese , Dept. of Comput. Sci. California Univ., Los Angeles, CA, USA
A.B. Kahng , Dept. of Comput. Sci. California Univ., Los Angeles, CA, USA
pp. 81-84

Statistical timing optimization of combinational logic circuits (PDF)

H.-F. Jyu , Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Malik , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 77-80

A path sensitization approach to area reduction (PDF)

H.-C. Chen , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
S. Cheng , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Y.-C. Hsu , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
D.H.C. Du , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 73-76

An analysis of path sensitization criteria (PDF)

J.P.M. Silva , Michigan Univ., MI, USA
K.A. Sakallah , Michigan Univ., MI, USA
pp. 68-72

AMBIANT: automatic generation of behavioral modifications for testability (PDF)

P. Vishakantaiah , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
T. Thomas , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
J.A. Abraham , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 63-66

Towards a methodology for the formal hierarchical verification of RISC processors (PDF)

S. Tahar , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 58-62

Hardware verification using symbolic state transition graphs (PDF)

P. Chen , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 54-57

An intelligent I-cache prefetch mechanism (PDF)

H.C. Young , IBM Almaden Res. Center, San Jose, CA, USA
E.J. Shekita , IBM Almaden Res. Center, San Jose, CA, USA
pp. 44-49

A split data cache for superscalar processors (PDF)

R. Boleyn , Dept. of Electr. Eng., Princeton Univ., NJ, USA
J. Debardelaben , Dept. of Electr. Eng., Princeton Univ., NJ, USA
V. Tiwari , Dept. of Electr. Eng., Princeton Univ., NJ, USA
A. Wolfe , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 32-39

The structure of assignment, precedence, and resource constraints in the ILP approach to the scheduling problem (PDF)

S. Chaudhuri , Rensselaer Polytech. Inst., Troy, NY, USA
R.A. Walker , Rensselaer Polytech. Inst., Troy, NY, USA
J. Mitchell , Rensselaer Polytech. Inst., Troy, NY, USA
pp. 25-29

Lower bounds on the iteration time and the number of resources for functional pipelined data flow graphs (PDF)

Y. Hu , Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
A. Ghouse , Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
B.S. Carlson , Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
pp. 21-24

A recursive technique for computing lower-bound performance of schedules (PDF)

M. Langevin , Dep. d'IRO, Montreal Univ., Que., Canada
E. Cerny , Dep. d'IRO, Montreal Univ., Que., Canada
pp. 16-20

Wearable computers: Merging information space with the workspace (PDF)

D.P. Siewiorek , Design for Manuf. Lab., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 10-11

Symbolic analysis methods for masks, circuits and systems (PDF)

R.E. Bryant , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 6-8
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