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Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors (1992)
Cambridge, MA, USA
Oct. 11, 1992 to Oct. 14, 1992
ISBN: 0-8186-3110-4
TABLE OF CONTENTS

Design and test-the next problems (PDF)

G.D. Robinson , GenRad Inc., Concord, MA, USA
pp. 10

High level design: a design vision for the 90's (PDF)

A.J. de Geus , Synopsys Inc., Mountain View, CA, USA
pp. 8

Field-programmable integrated circuits-overview and future trends (PDF)

A. El Gamal , Inf. Syst. Lab., Stanford Univ., CA, USA
pp. 2

An application specific processor for a multi-system navigation receiver (PDF)

E. Aardoom , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
P. Stravers , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 128-131

Design and implementation of a robot control system using a unified hardware-software rapid-prototyping framework (PDF)

M.B. Srivastava , EECS Dept., California Univ., Berkeley, CA, USA
T.I. Blumenau , EECS Dept., California Univ., Berkeley, CA, USA
R.W. Brodersen , EECS Dept., California Univ., Berkeley, CA, USA
pp. 124-127

Modified Booth algorithm for high radix multiplication (PDF)

P.E. Madrid , Motorola Inc., Austin, TX, USA
B. Millar , Motorola Inc., Austin, TX, USA
pp. 118-121

Reliable floating-point arithmetic algorithms for Berger encoded operands (PDF)

J.-C. Lo , Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA
pp. 110-113

Arithmetic error analysis of a new reciprocal cell (PDF)

V.K. Jain , Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
G.E. Perez , Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
pp. 106-109

Improving FPGA routing architectures using architecture and CAD interactions (PDF)

B. Tseng , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
J. Rose , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
S. Brown , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
pp. 99-104

Routable technology mapping for LUT FPGAs (PDF)

N.B. Bhat , Dept. of EECS, California Univ., Berkeley, CA, USA
pp. 95-98

Placement-based partitioning for lookup-table-based FPGAs (PDF)

S. Trimberger , Xilinx Inc., San Jose, CA, USA
M.-R. Chene , Xilinx Inc., San Jose, CA, USA
pp. 91-94

Routability-driven technology mapping for lookup table-based FPGAs (PDF)

M. Schlag , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
J. Kong , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
P.K. Chan , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 86-90

Implementing a high-frequency pattern generator based on combinational merging (PDF)

C.A. Zukowski , Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
Y.-W. Bai , Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
pp. 81-84

A comparison of self-timed design using FPGA, CMOS, and GaAs technologies (PDF)

E. Brunvand , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
N. Michell , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
K. Smith , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
pp. 76-80

Design of concurrent error-detectable VLSI-based array dividers (PDF)

Thou-Ho Chen , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Liang-Gee Chen , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Yi-Shing Chang , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 72-75

VLSI design of modulo adders/subtractors (PDF)

G. Lakhani , Texas Tech. Univ., Lubbock, TX, USA
pp. 68-71

Designing ASICs for use with multichip modules (PDF)

J. Banker , Environ. Res. Inst. of Michigan, Ann Arbor, MI, USA
pp. 54-58

Algorithms for interface timing verification (PDF)

K.L. McMillan , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 48-51

Fanin ordering in multi-shot timing analysis (PDF)

L.P.P.P. van Ginneken , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 44-47

Fast minimization of mixed-polarity AND/XOR canonical networks (PDF)

M.A. Perkowski , Portland State Univ., OR, USA
L. Csanky , Portland State Univ., OR, USA
A. Sarabi , Portland State Univ., OR, USA
I. Schafer , Portland State Univ., OR, USA
pp. 33-36

Behavioral synthesis for easy testability in data path allocation (PDF)

T.C. Lee , Dept. of Electr. Eng., Princeton Univ., NJ, USA
W.F. Wolf , Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 29-32

Identification of single gate delay fault redundancies (PDF)

D. Brand , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
V.S. Iyengar , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 24-28

Tutorial on embedded system design (PDF)

W. Wolf , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 18-21

Some techniques for efficient symbolic simulation-based verification (PDF)

P. Jain , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
G. Gopalakrishnan , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
pp. 598-602

RTL design verification by making use of datapath information (PDF)

M. Fujita , Fujitsu Labs. Ltd., Kawasaki, Japan
pp. 592-597

Comparing layouts with HDL models: a formal verification technique (PDF)

T. Kam , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 588-591

Repair of RAMs with clustered faults (PDF)

B. Vinnakota , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
J. Andrews , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 582-585

An ultra-large capacity single-chip memory architecture with self-testing and self-repairing (PDF)

T. Chen , Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
G. Sunada , Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
pp. 576-581

A tool for automatic generation of BISTed and transparent BISTed RAMs (PDF)

O. Kebichi , IMAG, Grenoble, France
M. Nicolaidis , IMAG, Grenoble, France
pp. 570-575

ALMP: a shifting memory architecture for loop pipelining (PDF)

H.F. Ugurdag , Dept. of Electr. Eng. & Appl. Phys., Case Western Reserve Univ., Cleveland, OH, USA
C.A. Papachristou , Dept. of Electr. Eng. & Appl. Phys., Case Western Reserve Univ., Cleveland, OH, USA
pp. 564-568

A CRegs implementation study based on the MIPS-X RISC processor (PDF)

S. Nowakowski , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
M.T. O'Keefe , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 558-563

Sampling of cache congruence classes (PDF)

L. Liu , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
J.-K. Peir , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 552-557

ProperCAD: a portable object-oriented parallel environment for VLSI CAD (PDF)

B. Ramkumar , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
P. Banerjee , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 544-548

High-level state machine specification and synthesis (PDF)

A. Kuehlmann , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R.A. Bergamaschi , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 536-539

Verification of I/O trace set inclusion for a class of non-deterministic finite state machines (PDF)

E. Cerny , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
pp. 526-530

Protocol verification as a hardware design aid (PDF)

D.L. Dill , Comput. Syst. Lab., Stanford Univ., CA, USA
A.J. Drexler , Comput. Syst. Lab., Stanford Univ., CA, USA
A.J. Hu , Comput. Syst. Lab., Stanford Univ., CA, USA
C.H. Yang , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 522-525

A C/sup ++/ based environment for analog circuit simulation (PDF)

B. Melville , AT&T Bell Labs., Murray Hill, NJ, USA
P. Feldmann , AT&T Bell Labs., Murray Hill, NJ, USA
S. Moinian , AT&T Bell Labs., Murray Hill, NJ, USA
pp. 516-519

NSC's digital answering machines solution (PDF)

O. Falik , Nat. Semicond. Ltd., Herzelia, Israel
G. Intrater , Nat. Semicond. Ltd., Herzelia, Israel
pp. 132-137

The future of embedded system design (PDF)

J. Aylor , Virginia Univ., Charlottesville, VA, USA
pp. 144-146

System level verification of large scale computer (PDF)

T. Okabayashi , Hitachi Ltd., Kanagawa, Japan
K. Kubo , Hitachi Ltd., Kanagawa, Japan
Z. Hirose , Hitachi Ltd., Kanagawa, Japan
K. Suzuki , Hitachi Ltd., Kanagawa, Japan
pp. 149-152

An improved graph-based FPGA technology mapping algorithm for delay optimization (PDF)

J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Y. Ding , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
A.B. Kahng , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
P. Trajmar , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 154-158

Technology mapping via transformations of function graphs (PDF)

S.-C. Chang , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
M. Marek-Sadowska , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 159-162

Synthesis on multiplexer-based FPGA using binary decision diagrams (PDF)

T. Besson , Inst. Nat. Polytech. de Grenoble, France
H. Bouzouzou , Inst. Nat. Polytech. de Grenoble, France
M. Crastes , Inst. Nat. Polytech. de Grenoble, France
I. Floricica , Inst. Nat. Polytech. de Grenoble, France
G. Saucier , Inst. Nat. Polytech. de Grenoble, France
pp. 163-167

MARVLE: a VLSI chip for variable length encoding and decoding (PDF)

A. Mukherjee , Dept. of Comput. Sci., Central Florida Univ., Orlando, FL, USA
pp. 170-173

Synthesis of multiple bus/functional unit architectures implementing neural networks (PDF)

B. Haroun , Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
E. Torbey , Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
pp. 174-178

One-chip system integration for GSM and the DSP KISS-16V2 (PDF)

G. Mahlich , Philips Kommunikations Ind. AG, Nuernburg, Germany
G.-H. Huaman-Bollo , Philips Kommunikations Ind. AG, Nuernburg, Germany
J. Preissner , Philips Kommunikations Ind. AG, Nuernburg, Germany
J. Schuck , Philips Kommunikations Ind. AG, Nuernburg, Germany
H. Sahm , Philips Kommunikations Ind. AG, Nuernburg, Germany
P. Weingart , Philips Kommunikations Ind. AG, Nuernburg, Germany
D. Weinsziehr , Philips Kommunikations Ind. AG, Nuernburg, Germany
J. Yeandel , Philips Kommunikations Ind. AG, Nuernburg, Germany
pp. 179-182

Interconnect modeling and design in high-speed VLSI/ULSI systems (PDF)

S.-Y. Oh , Hewlett Packard, Palo Alto, CA, USA
K.-J. Chang , Hewlett Packard, Palo Alto, CA, USA
N. Chang , Hewlett Packard, Palo Alto, CA, USA
K. Lee , Hewlett Packard, Palo Alto, CA, USA
pp. 184-189

Fully differential optical interconnects for high-speed digital systems (PDF)

C.-S. Li , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
H.S. Stone , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 190-193

Addressing the tradeoff between standard and custom ICs in system level design (PDF)

J.K. Adams , ECE Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
D.E. Thomas , ECE Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 194-197

IBM single chip RISC processor (RSC) (PDF)

C.R. Moore , IBM Corp., Austin, TX, USA
D.M. Balser , IBM Corp., Austin, TX, USA
J.S. Muhich , IBM Corp., Austin, TX, USA
R.E. East , IBM Corp., Austin, TX, USA
pp. 200-204

The T9000 transputer (PDF)

D. May , Inmos Ltd., Bristol, UK
R. Shepherd , Inmos Ltd., Bristol, UK
P. Thompson , Inmos Ltd., Bristol, UK
pp. 209-212

Electromagnetic modeling and simulation of electronic packages (PDF)

R. Mittra , Illinois Univ., Urbana, IL, USA
pp. 214-217

Three dimensional circuit oriented electromagnetic modeling for VLSI interconnects (PDF)

H. Heeb , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
A.E. Ruehli , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 218-221

Directions in future high end processors (PDF)

G.A. Sai-Halasz , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 230-233

Design and scaling of BiCMOS circuits (PDF)

P. Raje , Hewlett Packard Lab., Palo Alto, CA, USA
pp. 234-238

DACCT-dynamic ACCess testing of IBM large systems (PDF)

J.I. Alter , IBM Corp., Poughkeepsie, NY, USA
pp. 240-244

Constraint solving for test case generation: a technique for high-level design verification (PDF)

A.K. Chandra , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
V.S. Iyengar , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 245-248

Archimedes: an approach to architecture-independent modeling for high-level simulation (PDF)

M. Odawara , Hitachi Ltd., Tokyo, Japan
K. Kiriyama , Hitachi Ltd., Tokyo, Japan
T. Bandoh , Hitachi Ltd., Tokyo, Japan
pp. 249-254

Concurrent test scheduling in built-in self-test environment (PDF)

C.-I.H. Chen , Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
J.T. Yuen , Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
pp. 256-259

BIST generators for sequential faults (PDF)

S. Zhang , Dept. of Comput. Sci., Victoria Univ., BC, Canada
R. Byrne , Dept. of Comput. Sci., Victoria Univ., BC, Canada
D.M. Miller , Dept. of Comput. Sci., Victoria Univ., BC, Canada
pp. 260-263

Autonomous-tool for hardware partitioning in a built-in self-test environment (PDF)

C.-I.H. Chen , Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
J. Yuen , Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
J.-D. Lee , Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
pp. 264-267

Delay models for verifying speed-dependent asynchronous circuits (PDF)

J.R. Burch , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 270-274

Linear programming for optimum hazard elimination in asynchronous circuits (PDF)

L. Lavagno , Dept. of EECS, California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of EECS, California Univ., Berkeley, CA, USA
pp. 275-278

Synthesis of timed asynchronous circuits (PDF)

C. Myers , Comput. Syst. Lab., Stanford Univ., CA, USA
T.H.-Y. Meng , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 279-284

High-level synthesis of self-recovering microarchitectures (PDF)

A. Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
R. Karri , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 286-289

Estimating lower-bound performance of schedules using a relaxation technique (PDF)

M. Rim , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
R. Jain , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 290-294

Just in time scheduling (PDF)

K. Van Rompaey , IMEC Lab., Leuven, Belgium
I. Bolsens , IMEC Lab., Leuven, Belgium
H. De Man , IMEC Lab., Leuven, Belgium
pp. 295-300

NVAX and NVAX+: single-chip CMOS VAX microprocessors (PDF)

D. Bernstein , Digital Equipment Corp., Hudson, MA, USA
J.F. Brown , Digital Equipment Corp., Hudson, MA, USA
R.L. Stamm , Digital Equipment Corp., Hudson, MA, USA
G.M. Uhler , Digital Equipment Corp., Hudson, MA, USA
pp. 302-305

Logical verification of the NVAX CPU chip design (PDF)

W. Anderson , Digital Equipment Corp., Hudson, MA, USA
pp. 306-309

Design methodology and CAD tools for the NVAX microprocessor (PDF)

V. Peng , Digital Equipment Corp., Hudson, MA, USA
D.R. Donchin , Digital Equipment Corp., Hudson, MA, USA
Y.-T. Yen , Digital Equipment Corp., Hudson, MA, USA
pp. 310-313

State assignment algorithms for parallel controller synthesis (PDF)

J. Pardey , Dept. of Electr. & Electron. Eng., Bristol Univ., UK
T. Kozlowski , Dept. of Electr. & Electron. Eng., Bristol Univ., UK
J. Saul , Dept. of Electr. & Electron. Eng., Bristol Univ., UK
pp. 316-319

Finite state machine decomposition using multiway partitioning (PDF)

M.K. Yajnik , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
M.J. Ciesielski , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 320-323

The role of prime compatibles in the minimization of finite state machines (PDF)

J.-K. Rho , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
F. Somenzi , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 324-327

Sequential circuit design using synthesis and optimization (PDF)

E.M. Sentovich , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
K.J. Singh , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
C. Moon , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
H. Savoj , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 328-333

Dynamic reordering of high latency transactions using a modified micropipeline (PDF)

A. Liebchen , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
G. Gopalakrishnan , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
pp. 336-340

Practical asynchronous controller design (PDF)

S.M. Nowick , Comput. Syst. Lab., Stanford Univ., CA, USA
K.Y. Yun , Comput. Syst. Lab., Stanford Univ., CA, USA
D.L. Dill , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 341-345

Synthesis of 3D asynchronous state machines (PDF)

K.Y. Yun , Comput. Syst. Labs., Stanford Univ., CA, USA
D.L. Dill , Comput. Syst. Labs., Stanford Univ., CA, USA
S.M. Nowick , Comput. Syst. Labs., Stanford Univ., CA, USA
pp. 346-350

Register locking in an asynchronous microprocessor (PDF)

N.C. Paver , Dept. of Comput. Sci., Manchester Univ., UK
P. Day , Dept. of Comput. Sci., Manchester Univ., UK
S.B. Furber , Dept. of Comput. Sci., Manchester Univ., UK
J.D. Garside , Dept. of Comput. Sci., Manchester Univ., UK
J.V. Woods , Dept. of Comput. Sci., Manchester Univ., UK
pp. 351-355

On minimizing hardware overhead for pseudoexhaustive circuit testability (PDF)

D. Kagaris , Comput. Sci. Program, Dartmouth Coll., Hanover, NH, USA
F. Makedon , Comput. Sci. Program, Dartmouth Coll., Hanover, NH, USA
pp. 358-364

Fault simulation and test generation by fault sampling techniques (PDF)

S.A. Al-Arian , Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL, USA
M.A. Al-Kharji , Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL, USA
pp. 365-368

Multiple input bridging fault detection in CMOS sequential circuits (PDF)

N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
S.-J. Wang , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 369-372

Multiple fault detection in CMOS logic circuits (PDF)

D. Lu , Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
C.Q. Tong , Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
pp. 373-376

Channel density minimization by pin permutation (PDF)

Y. Cai , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 378-382

An area minimizer for floorplans with L-shaped regions (PDF)

Y. Sun , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
C.L. Liu , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 383-386

Workload-driven floorplanning for MIPS optimization (PDF)

P. Bose , IBM Thomas J. Watson, Res. Center, Yorktown Heights, NY, USA
D. LaPotin , IBM Thomas J. Watson, Res. Center, Yorktown Heights, NY, USA
G. Vijayan , IBM Thomas J. Watson, Res. Center, Yorktown Heights, NY, USA
S. Kim , IBM Thomas J. Watson, Res. Center, Yorktown Heights, NY, USA
pp. 387-391

Desktop wars: the PC versus the workstation (PDF)

N. Tredennick , Tredennick Inc., San Jose, CA, USA
pp. 394

On limitations and extensions of STG model for designing asynchronous control circuits (PDF)

A.V. Yakovlev , Dept. of Comput. Sci., Newcastle upon Tyne Univ., UK
pp. 396-400

Analysis of asynchronous binary arbitration on digital-transmission-line buses (PDF)

S. Kipnis , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 401-406

The Message Driven Processor: an integrated multicomputer processing element (PDF)

W.J. Dally , Artificial Intelligence Lab., MIT, Cambridge, MA, USA
A. Chien , Artificial Intelligence Lab., MIT, Cambridge, MA, USA
J.A.S. Fiske , Artificial Intelligence Lab., MIT, Cambridge, MA, USA
pp. 416-419

The J-machine network (PDF)

P.R. Nuth , Artificial Intelligence Lab., MIT, Cambridge, MA, USA
W.J. Dally , Artificial Intelligence Lab., MIT, Cambridge, MA, USA
pp. 420-423

MDP design tools and methods (PDF)

R.A. Lethin , MIT, Artificial Intelligence Lab., Cambridge, MA, USA
W.J. Dally , MIT, Artificial Intelligence Lab., Cambridge, MA, USA
pp. 424-428

Functional VLSI design verification methodology for the CM-5 massively parallel supercomputer (PDF)

M. St. Pierre , Thinking Machines Corp., Cambridge, MA, USA
S.-W. Yang , Thinking Machines Corp., Cambridge, MA, USA
D. Cassiday , Thinking Machines Corp., Cambridge, MA, USA
pp. 430-435

An IEEE 1149.1 compliant testability architecture with internal scan (PDF)

R.C. Zak , Thinking Machines Corp., Cambridge, MA, USA
J.V. Hill , Thinking Machines Corp., Cambridge, MA, USA
pp. 436-442

Modelling and simulation of design errors (PDF)

S. Kang , Comput. Eng. Res. Centre, Austin, TX, USA
pp. 443-446

On relationship between ITE and BDD (PDF)

W.K.C. Lam , Dept. of EECS, California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of EECS, California Univ., Berkeley, CA, USA
pp. 448-451

Boolean matching using binary decision diagrams with applications to logic synthesis and verification (PDF)

Y.-T. Lai , Dept. of EE-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 452-458

A synthesis algorithm for two-level XOR based circuits (PDF)

M.A. Heap , ECE Dept., Texas Univ., Austin, TX, USA
W.A. Rogers , ECE Dept., Texas Univ., Austin, TX, USA
M.R. Mercer , ECE Dept., Texas Univ., Austin, TX, USA
pp. 459-462

SYCLOP: synthesis of CMOS logic for low power applications (PDF)

K. Roy , Texas Instruments Inc., Dallas, TX, USA
S. Prasad , Texas Instruments Inc., Dallas, TX, USA
pp. 464-467

Delay prediction for technology-independent logic equations (PDF)

P.T. Gutwin , EECS Dept., California Univ., Berkeley, CA, USA
P.C. McGeer , EECS Dept., California Univ., Berkeley, CA, USA
R.K. Brayton , EECS Dept., California Univ., Berkeley, CA, USA
pp. 468-471

Library mapping of CMOS-switch-level-circuits by extraction of isomorphic subgraphs (PDF)

U. Westerholz , GMD/SET, St. Augustin, Germany
H.T. Vierhaus , GMD/SET, St. Augustin, Germany
pp. 472-475

Design of robust-path-delay-fault-testable combinational circuits by Boolean space expansion (PDF)

X. Xie , Dept. of Electr. Eng., Rochester Univ., NY, USA
A. Albicki , Dept. of Electr. Eng., Rochester Univ., NY, USA
A. Krasniewski , Dept. of Electr. Eng., Rochester Univ., NY, USA
pp. 482-485

Theory and design of two-rail totally self-checking basic building blocks (PDF)

Z.-J. Jiang , Fac. of Eng. & Appl. Sci., Memorial Univ. of Newfoundland, St. John's, Nfld., Canada
R. Venkatesan , Fac. of Eng. & Appl. Sci., Memorial Univ. of Newfoundland, St. John's, Nfld., Canada
pp. 486-489

The ETCA data-flow functional computer for real-time image processing (PDF)

G.M. Quenot , Lab. Syst. de Perception, DGA, Arcueil, France
B. Zavidovique , Lab. Syst. de Perception, DGA, Arcueil, France
pp. 492-495

EPGA and rapid prototyping technology use in a special purpose computer for molecular genetics (PDF)

B. Fagin , Thayer Sch. of Eng., Dartmouth Coll., Hanover, NH, USA
J.G. Watt , Thayer Sch. of Eng., Dartmouth Coll., Hanover, NH, USA
pp. 496-501

The selective extra-stage butterfly (PDF)

S. Konstantinidou , IBM Almaden Res. Center, San Jose, CA, USA
pp. 502-506

Distributed VLSI simulation on a network of workstations (PDF)

S. Karthik , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
J.A. Abraham , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 508-511

Hierarchical simulation of MOS circuits using extracted functional models (PDF)

J.A. Wehbeh , Center for Reliable & High-Performance Comput., Illinois Univ., Urbana, IL, USA
D.G. Saab , Center for Reliable & High-Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 512-515

An efficient logic emulation system (PDF)

M. Butts , Mento Graphics Corp., Wilsonville, OR, USA
J. Batcheller , Mento Graphics Corp., Wilsonville, OR, USA
J. Varghese , Mento Graphics Corp., Wilsonville, OR, USA
pp. 138-141
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