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Proceedings 1988 IEEE International Conference on Computer Design: VLSI (1988)
Rye Brook, NY, USA
Oct. 3, 1988 to Oct. 5, 1988
ISBN: 0-8186-0872-2
TABLE OF CONTENTS

A parallel simulated annealing algorithm for channel routing on a hypercube multiprocessor (PDF)

R.J. Brouwer , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
P. Banerjee , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 4-7

Object relocation in OX (PDF)

J.H. Kukula , IBM Corp., Poughkeepsie, NY, USA
pp. 8-10

Test generation in a parallel processing environment (PDF)

S.J. Chandra , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
J.H. Patel , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 11-14

Super computer technology at Convex (PDF)

H. Dozier , Convex Comput. Corp., Richardson, TX, USA
J. Gruger , Convex Comput. Corp., Richardson, TX, USA
pp. 16-20

The Cray Y-MP-a VLSI supercomputer (PDF)

S. Bowen , Cray Res. Inc., Chippewa Falls, WI, USA
pp. 21-23

The design of a reduced ambient temperature, air cooled supercomputer (PDF)

D.R. Mullen , Evans & Sutherland, Mountain View, CA, USA
G. Fernald , Evans & Sutherland, Mountain View, CA, USA
pp. 24-29

Comparative analysis of approaches to hardware acceleration for sparse-matrix factorization (PDF)

P. Sadayappan , Dept. of Comput. & Inf. Sci., Ohio State Univ., Columbus, OH, USA
pp. 32-35

Sorting on an array of processors (PDF)

H.V. Jagadish , AT&T Bell Labs., Murray Hill, NJ, USA
pp. 36-39

Floating point CORDIC for matrix computations (PDF)

J.R. Cavallaro , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
pp. 40-42

Analog circuit synthesis and exploration in OASYS (PDF)

R. Harjani , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
R.A. Rutenbar , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
L.R. Carley , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 44-47

Knowledge-based analog circuit synthesis with flexible architecture (PDF)

A.H. Fung , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
D.J. Chen , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Y.-N. Li , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
B.J. Sheu , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
pp. 48-51

Interconnection delay in very high-speed VLSI (PDF)

D. Zhou , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
F.P. Preparata , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
S.M. Kang , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 52-55

Test generation by fault sampling (PDF)

V.D. Agrawal , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 58-61

Adaptative backtrace and dynamic partitioning enhance ATPG (IC testing) (PDF)

A. Lioy , Dept. of Autom. & Inf., Polytech. of Turin, Italy
pp. 62-65

The BACK algorithm for sequential test generation (PDF)

W.-T. Cheng , AT&T Eng. Res. Center, Princeton, NJ, USA
pp. 66-69

Random testability analysis: comparing and evaluating existing approaches (PDF)

P. Camurati , Dept. of Autom. & Inf., Polytech. of Turin, Italy
P. Prinetto , Dept. of Autom. & Inf., Polytech. of Turin, Italy
M.S. Reorda , Dept. of Autom. & Inf., Polytech. of Turin, Italy
pp. 70-73

Multi-chip packaging for high performance systems (PDF)

C.C. Chao , Hewlett Packard Co., Palo Alto, CA, USA
K.H. Chen , Hewlett Packard Co., Palo Alto, CA, USA
R. Kaw , Hewlett Packard Co., Palo Alto, CA, USA
J. Leibovitz , Hewlett Packard Co., Palo Alto, CA, USA
V.K. Nagesh , Hewlett Packard Co., Palo Alto, CA, USA
K.D. Scholz , Hewlett Packard Co., Palo Alto, CA, USA
pp. 76-81

Modeling and simulation of coupled lossy lines for VLSI interconnections (PDF)

O.A. Palusinski , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
A.C. Cangellaris , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
J.L. Prince , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
J.C. Liao , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
L. Vakanis , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
pp. 82-86

Computer-aided simulation of optical interconnects for high-speed digital systems (PDF)

A.T. Yang , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
D.S. Gao , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
S.M. Kang , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 87-90

Free-space optical crossover interconnects for parallel computers (PDF)

J. Jahns , AT&T Bell Lab., Holmdel, NJ, USA
pp. 91-94

Instruction reorganization for a variable-length pipelined microprocessor (PDF)

S. Abraham , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 96-101

The capability mechanism of a VLSI processor (PDF)

K. Ghose , Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
pp. 106-109

Design tradeoffs for a 40 MIPS (peak) CMOS 32-bit microprocessor (PDF)

D.K. Lewis , GE Aerosp. Lab., Syracuse, NY, USA
J.P. Costello , GE Aerosp. Lab., Syracuse, NY, USA
pp. 110-113

Extension of a transistor level digital timing simulator to include first order analog behavior (PDF)

R. Chadha , AT&T Bell Lab., Murray Hill, NJ, USA
C.-F. Chen , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 116-119

MILES: a mixed level simulator for analog/digital design (PDF)

A.C.J. Stroucken , Philips Res. Lab., Eindhoven, Netherlands
G.J.J.M. van de Ven , Philips Res. Lab., Eindhoven, Netherlands
pp. 120-123

Variable reduction in MOS timing models (PDF)

C. Zukowski , Columbia Univ., New York, NY, USA
pp. 124-128

Parallel LU factorization for circuit simulation on an MIMD computer (PDF)

C.-C. Chen , Dept. of Electr. Eng., Southern Methodist Univ., Dallas, TX, USA
pp. 129-132

A class of fault-tolerant cellular permutation networks (PDF)

M. Eleuldj , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
E.M. Aboulhamid , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
E. Cerny , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
pp. 136-139

Test generation of C-testable array dividers (PDF)

C.-L. Wey , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
S.-M. Chang , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
pp. 140-144

Testing of VLSI regular arrays (PDF)

W.P. Marnane , Dept. of Eng. Sci., Oxford Univ., UK
W.R. Moore , Dept. of Eng. Sci., Oxford Univ., UK
pp. 145-148

VLSI programming and silicon compilation-a novel approach from Philips research (PDF)

C. Niessen , Philips Res. Labs., Eindhoven, Netherlands
C.H. van Berkel , Philips Res. Labs., Eindhoven, Netherlands
M. Rem , Philips Res. Labs., Eindhoven, Netherlands
R.W.J.J. Saeijs , Philips Res. Labs., Eindhoven, Netherlands
pp. 150-151

VLSI programming (PDF)

C.H. van Berkel , Philips Res. Lab., Eindhoven, Netherlands
M. Rem , Philips Res. Lab., Eindhoven, Netherlands
R.W.J.J. Saeijs , Philips Res. Lab., Eindhoven, Netherlands
pp. 152-156

Compilations of communicating processes into delay-insensitive circuits (PDF)

C.H. van Berkel , Philips Res. Lab., Eindhoven, Netherlands
R.W.J.J. Saeijs , Philips Res. Lab., Eindhoven, Netherlands
pp. 157-162

The design of the VLSI image-generator ZaP (PDF)

R.W.J.J. Saeijs , Philips Res. Lab., Eindhoven, Netherlands
C.H. van Berkel , Philips Res. Lab., Eindhoven, Netherlands
pp. 163-166

Tera-Hertz study of normal and superconducting transmission lines (PDF)

C.C. Chi , IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
D. Grischkowsky , IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 168-171

Automatic layout and optimization of static CMOS cells (PDF)

F. Mailhot , Dept. of Electr. Eng., Stanford Univ., Palo Alto, CA, USA
G. DeMicheli , Dept. of Electr. Eng., Stanford Univ., Palo Alto, CA, USA
pp. 180-185

Optimization for automatic cell assembly (PDF)

D.P. Dutt , AT&T Bell Lab., Allentown, PA, USA
G. Lakhani , AT&T Bell Lab., Allentown, PA, USA
pp. 186-189

An octagonal geometry compactor (PDF)

P.K. Sun , Control Data Corp., Minneapolis, MN, USA
pp. 190-193

Processor design using path programmable logic (PDF)

J.K. Flanagan , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
B.E. Nelson , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
pp. 196-199

Direct synthesis of mapping circuits (PDF)

L. Diaz-Olavarrieta , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
S.G. Zaky , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
pp. 200-203

SID: synthesis of integral design (PDF)

D.F. Hooper , Digital Equip. Corp., Marlboro, MA, USA
pp. 204-208

The KARL/KARATE system-integrating functional test development into a CAD environment for VLSI (PDF)

G. Alfs , Inf. Dept., Kaiserslautern Univ., West Germany
R.W. Hartenstein , Inf. Dept., Kaiserslautern Univ., West Germany
A. Wodtko , Inf. Dept., Kaiserslautern Univ., West Germany
pp. 209-212

Design of a high-speed arithmetic datapath (PDF)

M. Birman , Weitek, Sunnyvale, CA, USA
G. Chu , Weitek, Sunnyvale, CA, USA
L. Hu , Weitek, Sunnyvale, CA, USA
J. McLeod , Weitek, Sunnyvale, CA, USA
N. Bedard , Weitek, Sunnyvale, CA, USA
F. Ware , Weitek, Sunnyvale, CA, USA
L. Torban , Weitek, Sunnyvale, CA, USA
C.M. Lim , Weitek, Sunnyvale, CA, USA
pp. 214-215

Generation of high speed CMOS multiplier-accumulators (PDF)

K.F. Pang , LSI Logic Corp., Palo Alto, CA, USA
H.-W. Soong , LSI Logic Corp., Palo Alto, CA, USA
R. Sexton , LSI Logic Corp., Palo Alto, CA, USA
P.-H. Ang , LSI Logic Corp., Palo Alto, CA, USA
pp. 217-220

Approaching a nanosecond: a 32 bit adder (PDF)

G. Bewick , Comput. Syst. Lab., Stanford Univ., CA, USA
P. Song , Comput. Syst. Lab., Stanford Univ., CA, USA
G. De Micheli , Comput. Syst. Lab., Stanford Univ., CA, USA
M.J. Flynn , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 221-226

A comparison of two digit serial VLSI adders (PDF)

M.J. Irwin , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
pp. 227-229

System interface of the NS32532 microprocessor (PDF)

Y. Sidi , Nat. Semicond. Ltd., Herzlia, Israel
B. Maytal , Nat. Semicond. Ltd., Herzlia, Israel
Z. Bikovsky , Nat. Semicond. Ltd., Herzlia, Israel
D. Biran , Nat. Semicond. Ltd., Herzlia, Israel
J. Levy , Nat. Semicond. Ltd., Herzlia, Israel
Y. Milstain , Nat. Semicond. Ltd., Herzlia, Israel
A. Ostrer , Nat. Semicond. Ltd., Herzlia, Israel
pp. 232-235

Limits of backplane bus design (PDF)

P.L. Borrill , Nat. Semicond. Corp., Santa Clara, CA, USA
pp. 236-239

VLSI support for copyback caching protocols on Futurebus (PDF)

P. Sweazey , Nat. Semicond. Corp., Santa Clara, CA, USA
pp. 240-246

CTP-A family of optimizing compilers for the NS32532 microprocessor (PDF)

C. Bendelac , Nat. Semicond. Corp. Ltd., Herzlia, Israel
G. Erlich , Nat. Semicond. Corp. Ltd., Herzlia, Israel
pp. 247-250

McMAP: a fast technology mapping procedure for multi-level logic synthesis (PDF)

R. Lisanke , Microelectron. Center of North Carolina, Research Triangle Park, NC, USA
pp. 252-256

Mapping properties of multi-level logic synthesis operations (PDF)

M.C. Lega , AT&T Bell Labs., Murray Hill, NJ, USA
pp. 257-261

A rule based logic reorganization system LORES/EX (PDF)

J. Ishikawa , Mitsubishi Electr. Corp., Kanagawa, Japan
H. Sato , Mitsubishi Electr. Corp., Kanagawa, Japan
M. Hiramine , Mitsubishi Electr. Corp., Kanagawa, Japan
K. Ishida , Mitsubishi Electr. Corp., Kanagawa, Japan
S. Oguri , Mitsubishi Electr. Corp., Kanagawa, Japan
Y. Kazuma , Mitsubishi Electr. Corp., Kanagawa, Japan
S. Murai , Mitsubishi Electr. Corp., Kanagawa, Japan
pp. 262-266

Transient fault behavior in a microprocessor-A case study (PDF)

P. Duba , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
R.K. Lyer , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 272-276

Classical fault analysis for MOS VLSI circuits (PDF)

B.L. Shing , Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA
M.A. Franklin , Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA
pp. 277-282

A new class of symmetric error correcting/unidirectional error detecting codes (PDF)

N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NY, USA
pp. 283-286

Large memory embedded ASICs (PDF)

T. Iizuka , Toshiba Corp., Kawasaki, Japan
T. Sakurai , Toshiba Corp., Kawasaki, Japan
J. Matsunaga , Toshiba Corp., Kawasaki, Japan
K. Maeguchi , Toshiba Corp., Kawasaki, Japan
pp. 292-295

Gate array technology (PDF)

C.J. Dell'Oca , LSI Logic Corp., Milpitas, CA, USA
pp. 296-299

The Cydra 5 computer system architecture (PDF)

M. Schlansker , Cydrome Inc., Milpitas, CA, USA
M. McNamara , Cydrome Inc., Milpitas, CA, USA
pp. 302-306

The Astronautics ZS-1 processor (PDF)

J.E. Smith , Astronaut. Corp. of America, Madison, WI, USA
G.E. Dermer , Astronaut. Corp. of America, Madison, WI, USA
B.D. Vanderwarn , Astronaut. Corp. of America, Madison, WI, USA
S.D. Klinger , Astronaut. Corp. of America, Madison, WI, USA
C.M. Rozewski , Astronaut. Corp. of America, Madison, WI, USA
D.L. Fowler , Astronaut. Corp. of America, Madison, WI, USA
K.R. Scidmore , Astronaut. Corp. of America, Madison, WI, USA
J.P. Laudon , Astronaut. Corp. of America, Madison, WI, USA
pp. 307-310

EXIST: an interactive VLSI architectural environment (PDF)

P.S. van der Meulen , Philips Res. Lab., Sunnyvale, CA, USA
M.-D. Huang , Philips Res. Lab., Sunnyvale, CA, USA
U. Bar-Gadda , Philips Res. Lab., Sunnyvale, CA, USA
E. Lee , Philips Res. Lab., Sunnyvale, CA, USA
P. Baltus , Philips Res. Lab., Sunnyvale, CA, USA
pp. 312-319

PARET; an integrated visual tool for the study of parallel systems (PDF)

K.M. Nichols , AT&T Bell Labs., Holmdel, NJ, USA
J.T. Edmark , AT&T Bell Labs., Holmdel, NJ, USA
pp. 320-323

Critic: a knowledge-based program for critiquing circuit designs (PDF)

R.L. Spickelmier , Electron. Res. Lab., California Univ., Berkeley, CA, USA
A.R. Newton , Electron. Res. Lab., California Univ., Berkeley, CA, USA
pp. 324-327

A proposed standard test bus and boundary scan architecture (PDF)

L. Whetsel , Texas Instrum. Inc., Plano, TX, USA
pp. 330-333

IEEE P1149 Proposed Standard Testability Bus-An update with case histories (PDF)

J. Turino , Logical Solutions Technol. Inc., Campbell, CA, USA
pp. 334-337

HIT: a standard constructional system for testability and maintainability (PDF)

B.R. Wilkins , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
pp. 338-341

High speed, low power CMOS transmitter-receiver system (PDF)

T.J. Gabara , AT&T Bell Labs., Allentown, PA, USA
D.W. Thompson , AT&T Bell Labs., Allentown, PA, USA
pp. 344-347

A high speed static CMOS PLA architecture (PDF)

W.E. Engeler , General Electric Co., Schenectady, NY, USA
M. Lowy , General Electric Co., Schenectady, NY, USA
J. Pedicone , General Electric Co., Schenectady, NY, USA
J. Bloomer , General Electric Co., Schenectady, NY, USA
J. Richotte , General Electric Co., Schenectady, NY, USA
D. Chan , General Electric Co., Schenectady, NY, USA
pp. 348-351

A matched-delay CMOS TDM multiplexer cell (PDF)

C. Zukowski , Columbia Univ., New York, NY, USA
K. Shum , Columbia Univ., New York, NY, USA
pp. 352-355

CREATE-LIFE: a design system for high performances VLSI circuits (PDF)

J. Labrousse , Philips Res. Lab., Sunnyvale, CA, USA
G.A. Slavenburg , Philips Res. Lab., Sunnyvale, CA, USA
pp. 356-360

Microarchitecture of the 80960 high-integration processors (PDF)

G. Hinton , Intel Corp., Hillsboro, OR, USA
K. Lai , Intel Corp., Hillsboro, OR, USA
R. Steck , Intel Corp., Hillsboro, OR, USA
pp. 362-365

The MIPS M2000 system (PDF)

T. Riordan , MIPS Comput. Syst. Inc., Sunnyvale, CA, USA
G.P. Grewal , MIPS Comput. Syst. Inc., Sunnyvale, CA, USA
S. Hsu , MIPS Comput. Syst. Inc., Sunnyvale, CA, USA
J. Kinsel , MIPS Comput. Syst. Inc., Sunnyvale, CA, USA
J. Libby , MIPS Comput. Syst. Inc., Sunnyvale, CA, USA
R. March , MIPS Comput. Syst. Inc., Sunnyvale, CA, USA
M. Mills , MIPS Comput. Syst. Inc., Sunnyvale, CA, USA
P. Ries , MIPS Comput. Syst. Inc., Sunnyvale, CA, USA
R. Scofield , MIPS Comput. Syst. Inc., Sunnyvale, CA, USA
pp. 366-369

RISC architecture of the M88000 (PDF)

C. Melear , Motorola, Austin, TX, USA
pp. 370-373

First 32-bit SPARC-based processors implemented in high-speed CMOS (PDF)

M. Namjoo , Sun Microsystem Inc., Mountain View, CA, USA
pp. 374-376

Synthesis from VHDL (PDF)

J.S. Lis , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
D.D. Gajski , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 378-381

Representation of control and timing behavior with applications to interface synthesis (PDF)

S.A. Hayati , Univ. of Southern California, Los Angeles, CA, USA
A.C. Parker , Univ. of Southern California, Los Angeles, CA, USA
pp. 382-387

A novel approach to the synthesis of practical datapath architectures using artificial intelligence techniques (PDF)

N.S.H. Brooks , Dept. of Electron. Syst. Eng., Essex Univ., Colchester, UK
R.J. Mack , Dept. of Electron. Syst. Eng., Essex Univ., Colchester, UK
pp. 388-391

UBIST version of the SYCO's control section compiler (PDF)

K. Torki , IMAG/TIM3, Grenoble, France
M. Nicolaidis , IMAG/TIM3, Grenoble, France
A.A. Jerraya , IMAG/TIM3, Grenoble, France
B. Courtois , IMAG/TIM3, Grenoble, France
pp. 392-396

Integrated design and test synthesis (PDF)

C.H. Gebotys , Dept. of Electr. Eng., Waterloo Univ., Ont., Canada
M.I. Elmasry , Dept. of Electr. Eng., Waterloo Univ., Ont., Canada
pp. 398-401

Estimation of area and performance overheads for testable VLSI circuits (Abstract)

J.R. Miles , Dept. of Electr. Eng. & Electron., Brunel Univ., Uxbridge, UK
A.P. Ambler , Dept. of Electr. Eng. & Electron., Brunel Univ., Uxbridge, UK
pp. 402-407

A modular scan-based testability system (PDF)

F. Brglez , Microelectron. Center of North Carolina, NC, USA
pp. 408-412

CESAR-A programmable high performance systolic array processor (PDF)

M. Toverud , Norwegian Defence Res. Establ., Kjeller, Norway
V. Anderson , Norwegian Defence Res. Establ., Kjeller, Norway
pp. 414-417

Reconfiguration strategies in VLSI processor arrays (PDF)

K.P. Belkhale , Coord. Sci. Lab., Illinois Univ., IL, USA
P. Banerjee , Coord. Sci. Lab., Illinois Univ., IL, USA
pp. 418-421

Parallel calculation of shortest paths in sparse graphs on a systolic array (PDF)

S. Bauer , Inst. of Network Theory & Circuit Des., Tech. Univ. Munich, West Germany
U. Schwiegelshohn , Inst. of Network Theory & Circuit Des., Tech. Univ. Munich, West Germany
pp. 422-425

Area evaluation metrics for transistor placement (PDF)

T. Shiple , Digital Equip. Corp., Hudson, MA, USA
pp. 428-433

VITAL: fully automatic placement strategies for very large semicustom designs (PDF)

R. Putatunda , GE Electron. Lab., Moorestown, NJ, USA
D. Smith , GE Electron. Lab., Moorestown, NJ, USA
M. Stebnisky , GE Electron. Lab., Moorestown, NJ, USA
C. Puschak , GE Electron. Lab., Moorestown, NJ, USA
pp. 434-439

Alternative strategies for applying min-cut to VLSI placement (PDF)

D. Hill , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 440-444

A global chip test implementation including built-in self-test (PDF)

A.C. Erdal , Signetics, Sunnyvale, CA, USA
P.A. Uszynski , Signetics, Sunnyvale, CA, USA
pp. 446-449

A testable PLA design with low overhead and ease of test generation (PDF)

J.-Y. Jou , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 450-453

Current sensing for built-in testing of CMOS circuits (PDF)

D.B.I. Feltham , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
P.J. Nigh , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
L.R. Carley , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
W. Maly , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 454-457

Aliasing errors in signature analysis testing of integrated circuits (PDF)

M. Damiani , Bologna Univ., Italy
P. Olivo , Bologna Univ., Italy
M. Favalli , Bologna Univ., Italy
B. Ricco , Bologna Univ., Italy
pp. 458-461

A coprocessor with supercomputer capabilities for personal computers (PDF)

W. Marwood , Defence Sci. & Technol. Organ., Salisbury, SA, Australia
A.P. Clarke , Defence Sci. & Technol. Organ., Salisbury, SA, Australia
pp. 468-471

A methodology for the control and custom VLSI implementation of large-scale Clos networks (PDF)

J.R. Heath , Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
E.A. Disch , Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
pp. 472-477

Set-associative dynamic random access memory (PDF)

S.A. Ward , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
R.C. Zak , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
pp. 478-483

Implementation of fast radix-4 division with operands scaling (PDF)

M.D. Ercegovac , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
T. Lang , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
R. Modiri , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 486-489

A serial-input serial-output bit-sliced convolver (PDF)

L. Dadda , Dept. of Electron., Politecnico di Milano, Italy
L. Breveglieri , Dept. of Electron., Politecnico di Milano, Italy
pp. 490-495

Use of redundant binary representation for fault-tolerant arithmetic array processors (PDF)

V. Piuri , Dept. of Electron., Politecnico di Milano, Italy
R. Stefanelli , Dept. of Electron., Politecnico di Milano, Italy
pp. 496-501

Parallel decomposition of multipliers modulo (2/sup n/+or-1) (PDF)

A. Skavantzos , Dept. of Electr. Eng., Louisiana State Univ., Baton Rouge, LA, USA
pp. 502-506

The POTATO chip architecture: a study in tradeoffs for signal processing chip design (PDF)

B. Sharma , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
R. Jain , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
M.A. Breuer , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
A.C. Parker , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
C. Raghavendra , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
C.Y. Tseng , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 508-513

Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor (PDF)

M.A. Breuer , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
A. Majumdar , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
C.S. Raghavendra , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
pp. 514-519

VLSI implementation of GSC architecture with a new ripple carry adder (PDF)

I.S. Reed , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
B. Sharma , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
M.T. Shih , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 520-523

Design of a 64-processor by 128-memory crossbar switching network (PDF)

R.F. Miracky , Microelectron. & Comput. Technol. Corp., Austin, TX, USA
A. Hartmann , Microelectron. & Comput. Technol. Corp., Austin, TX, USA
L.N. Smith , Microelectron. & Comput. Technol. Corp., Austin, TX, USA
S. Redfield , Microelectron. & Comput. Technol. Corp., Austin, TX, USA
U. Ghoshal , Microelectron. & Comput. Technol. Corp., Austin, TX, USA
B. Weigler , Microelectron. & Comput. Technol. Corp., Austin, TX, USA
pp. 526-532

Trace driven modelling and performance evaluation of tightly coupled multiprocessor systems (PDF)

K.-Q. Luc , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
S. Ong , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
E.C. Hu , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 533-536

A highly parallel processor with an instruction set including relational algebra (PDF)

P. Faudemay , MASI Lab., Paris Univ., France
D. Etiemble , MASI Lab., Paris Univ., France
J.-L. Bechennec , MASI Lab., Paris Univ., France
pp. 537-538

Simulated annealing on a multiprocessor (PDF)

R.D. Chamberlain , Dept. of Electr. Eng. & Comput. Sci., Washington Univ., St. Louis, MO, USA
M.N. Edelman , Dept. of Electr. Eng. & Comput. Sci., Washington Univ., St. Louis, MO, USA
M.A. Franklin , Dept. of Electr. Eng. & Comput. Sci., Washington Univ., St. Louis, MO, USA
E.E. Witte , Dept. of Electr. Eng. & Comput. Sci., Washington Univ., St. Louis, MO, USA
pp. 540-544

Error tolerance in parallel simulated annealing techniques (PDF)

R. Jayaraman , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 545-548

Stop criteria in simulated annealing (PDF)

R.H.J.M. Otten , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
L.P.P.P. van Ginneken , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 549-552

On fault tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors (PDF)

S.H. Hosseini , Dept. of Electr. Eng. & Comput. Sci., Wisconsin Univ., Milwaukee, WI, USA
pp. 554-559

A self-reconfiguration scheme for fault-tolerant VLSI processor arrays (PDF)

S. Pateras , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
J. Rajski , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 560-563

APES: an integrated system for behavioral design, simulation and evaluation of array processors (PDF)

F. Distante , Dept. of Electron., Politecnico di Milano, Italy
V. Pieuri , Dept. of Electron., Politecnico di Milano, Italy
pp. 568-572

Design of a 20 MHz 64-tap transversal filter (PDF)

C.C. Stearns , LSI Logic Corp., Palo Alto, CA, USA
D.A. Luthi , LSI Logic Corp., Palo Alto, CA, USA
P.A. Ruetz , LSI Logic Corp., Palo Alto, CA, USA
P.H. Ang , LSI Logic Corp., Palo Alto, CA, USA
pp. 574-577

A high performance CMOS chipset for FFT processors (PDF)

S. Shen , Honeywell Inc., Colorado Springs, CO, USA
S. Magar , Honeywell Inc., Colorado Springs, CO, USA
R. Aguilar , Honeywell Inc., Colorado Springs, CO, USA
G. Luikuo , Honeywell Inc., Colorado Springs, CO, USA
M. Fleming , Honeywell Inc., Colorado Springs, CO, USA
K. Rishavy , Honeywell Inc., Colorado Springs, CO, USA
K. Murphy , Honeywell Inc., Colorado Springs, CO, USA
C. Furman , Honeywell Inc., Colorado Springs, CO, USA
pp. 578-581

A novel VLSI architecture for the real-time implementation of 2-D signal processing systems (PDF)

S.-M. Park , Dept. of Electron. Comput. Eng., North Caroline State Univ., Raleigh, NC, USA
W.E. Alexander , Dept. of Electron. Comput. Eng., North Caroline State Univ., Raleigh, NC, USA
pp. 582-585

A GaAs vector memory system for signal processing (PDF)

T.A. Misko , McDonnell Douglas Astronaut. Co., Huntington Beach, CA, USA
pp. 586-589

A higher level hardware design verification (PDF)

A. Takahara , LSI Lab., NTT, Kanagawa, Japan
pp. 596-599

Proof and synthesis (PDF)

M.P. Fourman , Dept. of Electr. Eng., Brunel Univ., Uxbridge, UK
W.J. Palmer , Dept. of Electr. Eng., Brunel Univ., Uxbridge, UK
R.M. Zimmer , Dept. of Electr. Eng., Brunel Univ., Uxbridge, UK
pp. 600-603

Verifiable and executable theories of design for synthesizing correct hardware (PDF)

S.-K. Chin , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
K.J. Greene , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
pp. 604-610
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