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Proceedings of ICCAD International Conference on Computer Aided Design (1998)
San Jose, CA, USA
Nov. 8, 1998 to Nov. 12, 1998
ISBN: 1-58113-008-2
TABLE OF CONTENTS

Simulation of coupling capacitances using matrix partitioning (Abstract)

T.V. Nguyen , Austin Res. Lab., IBM, Austin, TX, USA
pp. 12-18

h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response (PDF)

Tao Lin , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 19-25

Wireplanning in logic synthesis (Abstract)

W. Gosti , Dept. of EECS, California Univ., Berkeley, CA, USA
pp. 26-33

Graph matching-based algorithms for FPGA segmentation design (PDF)

Yao-Wen Chang , Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 34-39

Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources (Abstract)

J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 40-45

Control generation for embedded systems based on composition of modal processes (PDF)

Pai Chou , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 46-53

Synthesis of BIST hardware for performance testing of MCM interconnections (Abstract)

R. Pendurkar , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 69-73

Using a single input to support multiple scan chains (PDF)

Kuen-Jong Lee , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 74-78

High-level variable selection for partial-scan implementation (Abstract)

F.F. Hsu , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 79-84

Reduced-order modelling of linear time-varying systems (Abstract)

J. Roychowdhury , Bell Labs, Murray Hill, NJ, USA
pp. 92-95

Implementation and use of SPFDs in optimizing Boolean networks (Abstract)

S. Sinha , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 103-110

Finding all simple disjunctive decompositions using irredundant sum-of-products forms (Abstract)

S. Minato , NTT Optical Network Syst. Labs, Kanagawa, Japan
pp. 111-117

On accelerating pattern matching for technology mapping (Abstract)

Y. Matsunaga , Fijitsu Labs. Ltd., Japan
pp. 118-123

A performance-driven layer assignment algorithm for multiple interconnect trees (Abstract)

P. Saxena , Strategic CAD Labs., Intel Corp., Hillsboro, OR, USA
pp. 124-127

Optimal 2-D cell layout with integrated transistor folding (Abstract)

A. Gupta , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 128-135

Integrating logic retiming and register placement (PDF)

Tzu Chieh Tien , Dept. of Comput. Sci., Tsinghua Univ., Beijing, China
pp. 136-139

Static compaction using overlapped restoration and segment pruning (Abstract)

S.K. Bommu , Comput. & Commun. Res. Labs., NEC Res. Inst., Princeton, NJ, USA
pp. 140-146

Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits (Abstract)

V. Boppana , Fujitsu Labs. of America Inc., Sunnyvale, CA, USA
pp. 147-154

A fast, accurate, and non-statistical method for fault coverage estimation (Abstract)

M.S. Hsiao , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
pp. 155-161

Simulation of high-Q oscillators (Abstract)

M. Gourary , NIISAPRAN, Acad. of Sci., Moscow, Russia
pp. 162-169

Phase noise in oscillators: DAEs and colored noise sources (PDF)

A. Demir , Bell Labs., Murray Hill, NJ, USA
pp. 170-177

High-order Nystrom schemes for efficient 3-D capacitance extraction (PDF)

S. Kapur , Lucent Technols., Bell Labs., Murray Hill, NJ, USA
pp. 178-185

Signature hiding techniques for FPGA intellectual property protection (Abstract)

J. Lach , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 186-189

Analysis of watermarking techniques for graph coloring problem (PDF)

Gang Qu , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 190-193

Estimating noise in RF systems (Abstract)

J. Roychowdhury , Bell Labs., Murray Hill, NJ, USA
pp. 199-202

Getting to the bottom of deep submicron (Abstract)

D. Sylvester , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 203-211

Determination of worst-case aggressor alignment for delay calculation (Abstract)

P.D. Gross , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 212-219

Noise considerations in circuit optimization (Abstract)

A.R. Conn , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 220-227

Energy-efficiency in presence of deep submicron noise (Abstract)

R. Hegde , Coordinated Sci. Lab./ECE Dept., Illinois Univ., Urbana, IL, USA
pp. 228-234

Domino logic synthesis using complex static gates (Abstract)

T. Thorp , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 242-247

Technology mapping for domino logic (PDF)

Min Zhao , Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 248-251

Slicing floorplans with pre-placed modules (Abstract)

F.Y. Young , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 252-258

Arbitrary rectilinear block packing based on sequence pair (Abstract)

M.Z. Kang , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 259-266

The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks (Abstract)

K. Sakanushi , Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
pp. 267-274

Test set compaction algorithms for combinational circuits (Abstract)

I. Hamzaoglu , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 283-289

A linear optimal test generation algorithm for interconnect testing (PDF)

Chauchin Su , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
pp. 290-295

GPCAD: a tool for CMOS op-amp synthesis (Abstract)

M. del Mar Hershenson , Dept. of Electr. Eng., Stanford Univ., CA, USA
pp. 296-303

Reencoding for cycle-time minimization under fixed encoding length (Abstract)

B. Iyer , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 312-315

Using precomputation in architecture and logic resynthesis (Abstract)

S. Hassoun , Tufts Univ., Medford, MA, USA
pp. 316-323

Approximate Reachability Don't Cares for CTL model checking (PDF)

In-Ho Moon , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 351-358

Adaptive variable reordering for symbolic model checking (Abstract)

G. Kamhi , Future CAD Technol., Intel Israel Ltd., Haifa, Israel
pp. 359-365

Verification by approximate forward and backward reachability (Abstract)

S.G. Govindaraju , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 366-370

CMOS analog circuit stack generation with matching constraints (Abstract)

R. Naiknaware , Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
pp. 371-375

CONCERT: a concurrent transient fault simulator for nonlinear analog circuits (PDF)

Junwei Hou , Sch. of Electr. & Compute Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 384-391

Waiting false path analysis of sequential logic circuits for performance optimization (Abstract)

K. Nakamura , Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
pp. 392-395

Asymptotically efficient retiming under setup and hold constraints (Abstract)

M.C. Papaefthymiou , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 396-401

Architecture driven circuit partitioning (PDF)

Chau-Shen Chen , Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 408-411

The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications (Abstract)

S. Nakatake , Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
pp. 418-425

Hardware/software co-synthesis with memory hierarchies (PDF)

Yanbing Li , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 430-436

Communication synthesis for distributed embedded systems (Abstract)

R.B. Ortega , Dept. of Comput. & Software Syst., Washington Univ., Bothell, WA, USA
pp. 437-444

Analysis of emerging core-based design lifecycle (PDF)

K. Kucukcakar , Escalade Corp., Santa Clara, CA, USA
pp. 445-449

Core integration: overview and challenges (Abstract)

E. Wein , LSI Logic, Pleasanton, CA, USA
pp. 450-452

Full-chip verification of UDSM designs (Abstract)

R. Saleh , Simplex Solutions, Sunnyvale, CA, USA
pp. 453-460

Node sampling: a robust RTL power modeling approach (Abstract)

A. Bogliolo , Dipt. di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
pp. 461-467

Estimation of power sensitivity in sequential circuits with power macromodeling application (PDF)

Zhanping Chen , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 468-472

Power invariant vector sequence compaction (Abstract)

A. Pinar , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 473-476

Efficient encoding for exact symbolic automata-based scheduling (Abstract)

S. Haynal , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 477-481

Static power optimization of deep submicron CMOS circuits for dual V/sub T/ technology (PDF)

Qi Wang , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
pp. 490-496

Network flow based circuit partitioning for time-multiplexed FPGAs (PDF)

Huiqun Liu , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 497-504

On multilevel circuit partitioning (Abstract)

S. Wichlund , Alcatel Telecom Norway AS, Oslo, Norway
pp. 505-511

Multiway partitioning with pairwise movement (PDF)

J. Gong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 512-516

Functional debugging of systems-on-chip (Abstract)

D. Kirovski , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 525-528

Proposal of a timing model for CMOS logic gates driving a CRC /spl pi/ load (PDF)

A. Hirata , Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan
pp. 537-544

Gate-size selection for standard cell libraries (Abstract)

F. Beeftink , Delft Univ. of Technol., Netherlands
pp. 545-550

Tight integration of combinational verification methods (Abstract)

J.R. Burch , Cadence Berkeley Labs., CA, USA
pp. 570-576

Period assignment in multidimensional periodic scheduling (Abstract)

W.F.J. Verhaegh , Philips Res. Lab., Eindhoven, Netherlands
pp. 585-592

Improving the computational performance of ILP-based problems (Abstract)

M. Narasimhan , Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA
pp. 593-596

Techniques for energy minimization of communication pipelines (PDF)

Gang Qu , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 597-600

PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsis (Abstract)

S. Roy , Ambit Design Syst., Santa Clara, CA, USA
pp. 601-606

Shaping a VLSI wire to minimize delay using transmission line model (PDF)

Youxin Gao , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 611-616

A simultaneous routing tree construction and fanout optimization algorithm (Abstract)

A.H. Salek , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 625-630

Sampling schemes for computing OBDD variable orderings (Abstract)

J. Jain , Fujitsu Labs. of America, Sunnyvale, CA, USA
pp. 631-638

The design of a cache-friendly BDD library (Abstract)

D.E. Long , Lucent Technol., Bell Labs., Murray Hill, NJ, USA
pp. 639-645

Design of experiments in BDD variable ordering: lessons learned (Abstract)

J.E. Harlow , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 646-652

On-line scheduling of hard real-time tasks on variable voltage processor (Abstract)

I. Hong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 653-656

Synthesis of application specific instructions for embedded DSP software (PDF)

Hoon Choi , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
pp. 665-671

Word-level decision diagrams, WLCDs and division (Abstract)

C. Scholl , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
pp. 672-677

Polynomial methods for component matching and verification (Abstract)

J. Smith , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 678-685

Symbolic model checking of process networks using interval diagram techniques (Abstract)

K. Strehl , Comput. Eng. & Networks Lab., Fed. Inst. of Technol., Zurich, Switzerland
pp. 686-692
Session 12B: Embedded Tutorial - Dynamic Power Management of Electronic Systems

Dynamic Power Management of Electronic Systems (Abstract)

Alessandro Bogliolo , DEIS - Universit? di Bologna
Giovanni De Micheli , CSL - Stanford University
Luca Benini , DEIS - Universit? di Bologna
pp. 696-702
Session 12A: Embedded Tutorial - Interface Synthesis: A Vertical Slice from Digital Logic to Software Components

Interface Synthesis: A Vertical Slice from Digital Logic to Software Components (Abstract)

Luciano Lavagno , Politecnico di Torino, Italia
Ross B. Ortega , University of Washington, Bothell
Gaetano Borriello , University of Washington, Seattle
pp. 693-695
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