The Community for Technology Leaders
1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers (1991)
Santa Clara, CA, USA
Nov. 11, 1991 to Nov. 14, 1991
ISBN: 0-8186-2157-5
TABLE OF CONTENTS

A cell-replicating approach to minicut-based circuit partitioning (PDF)

C. Kring , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A.R. Newton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 2-5

On clustering for minimum delay/ara (PDF)

R. Murgai , Dept. of EECS, California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of EECS, California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of EECS, California Univ., Berkeley, CA, USA
pp. 6-9

Fast spectral methods for ratio cut partitioning and clustering (PDF)

L. Hagen , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
A. Kahng , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 10-13

iMACSIM: a program for multi-level analog circuit simulation (PDF)

J. Singh , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
R. Saleh , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 16-19

A modified envelope-following approach to clocked analog circuit simulation (PDF)

L.M. Silveira , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
J. White , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
S. Leeb , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 20-23

An accelerated steady-state method for networks with internally controlled switches (PDF)

D. Bedrosian , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
J. Vlach , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
pp. 24-27

Automatic synthesis of time-stationary controllers for pipelined data paths (PDF)

J.J. Kim , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
F.J. Kurdahi , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
pp. 30-33

Layout-area models for high-level synthesis (PDF)

A.C.-H. Wu , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
V. Chaiyakul , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
D.D. Gajski , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 34-37

Efficient microcode arrangement and controller synthesis for application specific integrated circuits (PDF)

S.-Z. Lin , Dept. of Comput. Sci., California Univ., Riverside, CA, USA
C.-T. Hwang , Dept. of Comput. Sci., California Univ., Riverside, CA, USA
Y.-C. Hsu , Dept. of Comput. Sci., California Univ., Riverside, CA, USA
pp. 38-41

A new performance driven placement algorithm (PDF)

T. Gao , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
P.M. Vaidya , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
C.L. Liu , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 44-47

RITUAL: a performance driven placement algorithm for small cell ICs (PDF)

A. Srinivasan , Dept. of EECS, California Univ., Berkeley, CA, USA
K. Chaudhary , Dept. of EECS, California Univ., Berkeley, CA, USA
E.S. Kuh , Dept. of EECS, California Univ., Berkeley, CA, USA
pp. 48-51

Wafer packing for full mask exposure fabrication (PDF)

C.-T. Wu , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
A. Lim , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
D. Du , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 52-55

A floorplanning algorithm using rectangular Voronoi diagram and force-directed block shaping (PDF)

S.-G. Choi , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
C.-M. Kyung , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
pp. 56-59

An impulse-response based linear time-complexity algorithm for lossy interconnect simulation (PDF)

J.S. Roychowdhury , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A.R. Newton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
D.O. Pederson , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 62-65

Delay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations (PDF)

D.H. Xie , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
M. Nakhla , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
pp. 66-69

Retarded models for PC board interconnects-or how the speed of light affects your SPICE circuit simulation (PDF)

H. Heeb , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
A. Ruehli , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 70-73

Evaluating RC-interconnect using moment-matching approximations (PDF)

N. Gopal , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
D.P. Neikirk , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
L.T. Pillage , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 74-77

The effects of false paths in high-level synthesis (PDF)

R.A. Bergamaschi , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 80-83

A scheduling algorithm for conditional resource sharing (PDF)

T. Kim , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
J.W.S. Liu , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
C.L. Liu , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 84-87

Optimizing resource utilization using transformations (PDF)

M. Potkonjak , Dept. of EECS, California Univ., Berkeley, CA, USA
J. Rabaey , Dept. of EECS, California Univ., Berkeley, CA, USA
pp. 88-91

An algorithm for component selection in performance optimized scheduling (PDF)

L. Ramachandran , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
D.D. Gajski , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 92-95

Optimal module implementation and its application to transistor placement (PDF)

T.W. Her , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 98-101

Track assignment in the Pathway datapath layout assembler (PDF)

A.B. Cohen , National Semiconductor IC Ltd., Herzlia B., Israel
M. Shechory , National Semiconductor IC Ltd., Herzlia B., Israel
pp. 102-105

Flexible block-multiplier generation (PDF)

H.M.A.M. Arts , Design Autom. Sect., Eindhoven Univ. of Tech., Netherlands
J.T.J. van Eijndhoven , Design Autom. Sect., Eindhoven Univ. of Tech., Netherlands
pp. 106-109

Transient three-dimensional mixed-level circuit and device simulation: algorithms and applications (PDF)

K. Mayaram , Texas Instruments, Dallas, TX, USA
P. Yang , Texas Instruments, Dallas, TX, USA
J.-H. Chern , Texas Instruments, Dallas, TX, USA
pp. 112-115

Conjugate direction waveform methods for transient two-dimensional simulation of MOS devices (PDF)

A. Lumsdaine , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
M. Reichelt , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
J. White , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 116-119

Heuristic minimization of multiple-valued relations (PDF)

Y. Watanabe , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 126-129

LSAT-an algorithm for the synthesis of two level threshold gate networks (PDF)

A.L. Oliveira , Dept. of EECS, California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of EECS, California Univ., Berkeley, CA, USA
pp. 130-133

Layout driven logic restructuring/decomposition (PDF)

M. Pedram , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
N. Bhat , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 134-137

Data framework for VLSI design (PDF)

A. Milo , Motorola Semiconductor Israel Ltd., Tel-Aviv, Israel
S. Nehab , Motorola Semiconductor Israel Ltd., Tel-Aviv, Israel
pp. 140-143

SLIM: a system for ASIC library management (PDF)

M. Mehendale , Texas Instruments India Pvt. Ltd., Bangalore, India
P. Murugavel , Texas Instruments India Pvt. Ltd., Bangalore, India
M. Poornima , Texas Instruments India Pvt. Ltd., Bangalore, India
C.M. Nibhanupudi , Texas Instruments India Pvt. Ltd., Bangalore, India
A. Ghose , Texas Instruments India Pvt. Ltd., Bangalore, India
pp. 144-147

Estimating essential design characteristics to support project planning for ASIC design management (PDF)

K.D. Muller-Glaser , Inst. of Comput.-Aided Circuit Design, Erlangen Univ., Nurnberg, Germany
K. Kirsch , Inst. of Comput.-Aided Circuit Design, Erlangen Univ., Nurnberg, Germany
K. Neusinger , Inst. of Comput.-Aided Circuit Design, Erlangen Univ., Nurnberg, Germany
pp. 148-151

Rapid-prototyping of hardware and software in a unified framework (PDF)

M.B. Srivastava , EECS Dept., California Univ., Berkeley, CA, USA
R.W. Brodersen , EECS Dept., California Univ., Berkeley, CA, USA
pp. 152-155

New simulation methods for MOS VLSI timing and reliability (PDF)

Y.-H. Shih , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Y. Leblebici , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
S.M. Kang , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 162-165

Circuit optimization driven by worst-case distances (PDF)

K.J. Antreich , Inst. of Electron. Design Autom., Tech. Univ. of Munich, Germany
H.E. Graeb , Inst. of Electron. Design Autom., Tech. Univ. of Munich, Germany
pp. 166-169

Circuit performance variability reduction: principles, problems, and practical solutions (PDF)

M.A. Styblinski , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
J.C. Zhang , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 170-173

Timing analysis and delay-fault test generation using path-recursive functions (PDF)

P.C. McGeer , California Univ., Berkeley, CA, USA
A. Saldanha , California Univ., Berkeley, CA, USA
P.R. Stephan , California Univ., Berkeley, CA, USA
R.K. Brayton , California Univ., Berkeley, CA, USA
A.L. Sangiovanni-Vincentelli , California Univ., Berkeley, CA, USA
pp. 180-183

Performance enhancement through the generalized bypass transform (PDF)

P.C. McGeer , EECS Dept., California Univ., Berkeley, CA, USA
R.K. Brayton , EECS Dept., California Univ., Berkeley, CA, USA
A.L. Sangiovanni-Vincentelli , EECS Dept., California Univ., Berkeley, CA, USA
pp. 184-187

Delay optimization of combinational logic circuits by clustering and partial collapsing (PDF)

H.J. Touati , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
H. Savoj , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 188-191

DIATEST: a fast diagnostic test pattern generator for combinational circuits (PDF)

T. Gruning , Inst. fuer Theor. Elektrotech., Hannover Univ., Germany
U. Mahlstedt , Inst. fuer Theor. Elektrotech., Hannover Univ., Germany
H. Koopmeiners , Inst. fuer Theor. Elektrotech., Hannover Univ., Germany
pp. 194-197

Beta: behavioral testability analysis (PDF)

C.-H. Chen , Illinois Univ., Urbana, IL, USA
C. Wu , Illinois Univ., Urbana, IL, USA
D.G. Saab , Illinois Univ., Urbana, IL, USA
pp. 202-205

Path sensitization in critical path problem (PDF)

H.-C. Chen , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
D.H.C. Du , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 208-211

FPD-an environment for exact timing analysis (PDF)

J.P. Silva , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
K.A. Sakallah , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
L.M. Vidigal , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 212-215

A new approach to solving false path problem in timing analysis (PDF)

Shiang-Tang Huang , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Tai-Ming Parng , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 216-219

State assignment based on the reduced dependency theory and recent experimental results (PDF)

C. Duff , Inst. Nat. Polytech de Grenoble, France
G. Saucier , Inst. Nat. Polytech de Grenoble, France
pp. 222-225

A flexible scheme for state assignment based on characteristics of the FSM (PDF)

B. Mitra , Texas Instruments India Ltd., Bangalore, India
P.R. Panda , Texas Instruments India Ltd., Bangalore, India
pp. 226-229

Encoding multiple outputs for improved column compaction (PDF)

D. Binger , Dept. of Comput. Sci., Illinois Univ., IL, USA
D.W. Knapp , Dept. of Comput. Sci., Illinois Univ., IL, USA
pp. 230-233

Synthesis of optimal 1-hot coded on-chip controllers for BIST hardware (PDF)

D. Mukherjee , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
C. Njinda , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
M.A. Breuer , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 236-239

BISTSYN-a built-in self-test synthesizer (PDF)

C.-I.H. Chen , Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
pp. 240-243

Built-in self-test in multi-port RAMs (PDF)

A.V. Castro , IMAG/TIM3 Lab., Grenoble, France
M. Nicolaidis , IMAG/TIM3 Lab., Grenoble, France
pp. 248-251

The Hercules CAD task management system (PDF)

J.B. Brockman , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
S.W. Director , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 254-257

The configuration management for version control in an object-oriented VHDL design environment (PDF)

M.J. Chung , Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
S. Kim , Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
pp. 258-261

SADE: a graphical tool for VHDL-based system analysis (PDF)

J. Lahti , Dept. of Electr. Eng., Oulu Univ., Finland
M. Sipola , Dept. of Electr. Eng., Oulu Univ., Finland
J. Kivela , Dept. of Electr. Eng., Oulu Univ., Finland
pp. 262-265

System specification and synthesis with the SpecCharts language (PDF)

S. Narayan , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
F. Vahid , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
D.D. Gajski , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 266-269

Compiling multi-dimensional data streams into distributed DSP ASIC memory (PDF)

J. Vanhoof , IMEC, Heverlee, Belgium
I. Bolsens , IMEC, Heverlee, Belgium
pp. 272-275

Post-processor for data path synthesis using multiport memories (PDF)

I. Ahmad , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
C.Y.R. Chen , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
pp. 276-279

Clustering techniques for register optimization during scheduling preprocessing (PDF)

F. Depuydt , IMEC, Leuven, Belgium
G. Goossens , IMEC, Leuven, Belgium
H. De Man , IMEC, Leuven, Belgium
pp. 280-283

Scheduling in programmable video signal processors (PDF)

G. Essink , Philips Res., Eindhoven, Netherlands
E. Aarts , Philips Res., Eindhoven, Netherlands
R. van Dongen , Philips Res., Eindhoven, Netherlands
P. van Gerwen , Philips Res., Eindhoven, Netherlands
J. Korst , Philips Res., Eindhoven, Netherlands
K. Vissers , Philips Res., Eindhoven, Netherlands
pp. 284-287

Circuit comparison by hierarchical pattern matching (PDF)

G. Pelz , Fraunhofer-Inst. of Microelectron. Circuits & Syst., Duisburg, Germany
U. Roettcher , Fraunhofer-Inst. of Microelectron. Circuits & Syst., Duisburg, Germany
pp. 290-293

HIVE: an efficient interconnect capacitance extractor to support submicron multilevel interconnect designs (PDF)

K.-J. Chang , Hewlett-Parkard Co., Palo Alto, CA, USA
S.-Y. Oh , Hewlett-Parkard Co., Palo Alto, CA, USA
K. Lee , Hewlett-Parkard Co., Palo Alto, CA, USA
pp. 294-297

Automatic detection of MOS synchronizers for timing verification (PDF)

J. Grodstein , Digital Equipment Corp., Hudson, MA, USA
N. Rethman , Digital Equipment Corp., Hudson, MA, USA
R. Razdan , Digital Equipment Corp., Hudson, MA, USA
G. Bischoff , Digital Equipment Corp., Hudson, MA, USA
pp. 304-307

Static timing analysis using interval constraints (PDF)

R. Stewart , SGS-THOMSON Microelectron., Grenoble, France
J. Benkoski , SGS-THOMSON Microelectron., Grenoble, France
pp. 308-311

The calculation of signal stable ranges in combinational circuits (PDF)

L.-R. Liu , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
H.-C. Chen , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
D.H.C. Du , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 312-315

Automatic synthesis of locally-clocked asynchronous state machines (PDF)

S.M. Nowick , Comput. Syst. Lab., Stanford Univ., CA, USA
D.L. Dill , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 318-321

Synthesis of hazard-free asynchronous circuits from graphical specifications (PDF)

C.W. Moon , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
P.R. Stephan , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 322-325

Timing-oriented routers for PCB layout design of high-performance computers (PDF)

Y. Sekiyama , Hitachi Ltd., Ibaraki, Japan
Y. Fujihara , Hitachi Ltd., Ibaraki, Japan
T. Hayashi , Hitachi Ltd., Ibaraki, Japan
M. Seki , Hitachi Ltd., Ibaraki, Japan
J. Kusuhara , Hitachi Ltd., Ibaraki, Japan
K. Iijima , Hitachi Ltd., Ibaraki, Japan
pp. 332-335

Exact zero skew (PDF)

R.-S. Tsay , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 336-339

PROTON: a parallel detailed router on an MIMD parallel machine (PDF)

T. Yamauchi , NEC Corp., Kanagawa, Japan
T. Nakata , NEC Corp., Kanagawa, Japan
N. Koike , NEC Corp., Kanagawa, Japan
A. Ishizuka , NEC Corp., Kanagawa, Japan
N. Nishiguchi , NEC Corp., Kanagawa, Japan
pp. 340-343

A parallel Steiner heuristic for wirelength estimation of large net populations (PDF)

R. Jayaraman , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.A. Rutenbar , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 344-347

Bipolar timing modeling including interconnects based on parametric correction (PDF)

A.T. Yang , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Y.-H. Chang , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 354-357

A stimulus/response system based on hierarchical timing diagrams (PDF)

K. Khordoc , Dep. D'inf. et de Recherche Oper., Montreal Univ., Que., Canada
M. Dufresne , Dep. D'inf. et de Recherche Oper., Montreal Univ., Que., Canada
E. Cerny , Dep. D'inf. et de Recherche Oper., Montreal Univ., Que., Canada
pp. 358-361

Obtaining functionally equivalent simulations using VHDL and a time-shift transformation (PDF)

F. Vahid , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
D.D. Gajski , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 362-365

Converting combinational circuits into pipelined data paths (PDF)

A. Munzer , Lab. fuer Informationstechnol., Hannover Univ., Germany
G. Hemme , Lab. fuer Informationstechnol., Hannover Univ., Germany
pp. 368-371

An ATPG-based approach to sequential logic optimization (PDF)

K.-T. Cheng , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 372-375

Calculating resettability and reset sequences (PDF)

C. Pixley , Microelectronics & Computer Technology Corp., Austin, TX, USA
G. Beihl , Microelectronics & Computer Technology Corp., Austin, TX, USA
pp. 376-379

Verification of relations between synchronous machines (PDF)

F. Van Aelten , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
J. Allen , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
S. Devadas , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 380-383

A behavioral representation for Nyquist rate A/D converters (PDF)

E. Liu , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A.L. Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
G. Gielen , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
P.R. Gray , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 386-389

Automating analog circuit design using constrained optimization techniques (PDF)

P.C. Maulik , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L.R. Carley , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 390-393

Techniques for simultaneous placement and routing of custom analog cells in KOAN/ANAGRAM II (PDF)

J.M. Cohn , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D.J. Garrod , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.A. Rutenbar , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L.R. Carley , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 394-397

A fault oriented partial scan design approach (PDF)

V. Chickermane , Illinois Univ., Urbana, IL, USA
J.H. Patel , Illinois Univ., Urbana, IL, USA
pp. 400-403

Timing-driven partial scan (PDF)

J.-Y. Jou , AT&T Bell Lab., Murray Hill, NJ, USA
K.-T. Cheng , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 404-407

Ordering storage elements in a single scan chain (PDF)

R. Gupta , IBM East Fishkill, Hopewell Junction, NY, USA
pp. 408-411

Finite state machine decomposition by transition pairing (PDF)

J. Kukula , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
S. Devadas , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 414-417

Don't care sequences and the optimization of interacting finite state machines (PDF)

J.-K. Rho , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
G. Hachtel , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
F. Somenzi , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 418-421

An automatic finite state machine synthesis using temporal logic decomposition (PDF)

K. Bekki , Hitachi Ltd., Ibaraki, Japan
T. Nagai , Hitachi Ltd., Ibaraki, Japan
N. Hamada , Hitachi Ltd., Ibaraki, Japan
pp. 422-425

Algorithms for three-layer over-the-cell channel routing (PDF)

N.D. Holmes , Dept. of CS, Western Michigan Univ., Kalamazoo, MI, USA
N.A. Sherwani , Dept. of CS, Western Michigan Univ., Kalamazoo, MI, USA
pp. 428-431

A new model for over-the-cell channel routing with three layers (PDF)

M. Terai , Mitsubishi Electric Corp., Hyogo, Japan
K. Takahashi , Mitsubishi Electric Corp., Hyogo, Japan
K. Nakajima , Mitsubishi Electric Corp., Hyogo, Japan
K. Sato , Mitsubishi Electric Corp., Hyogo, Japan
pp. 432-435

A channel router for single layer customization technology (PDF)

Y. Sun , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
S.-k. Dong , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 436-439

A hierarchical methodology to improve channel routing by pin permutation (PDF)

C.Y. Hou , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
C.Y.R. Chen , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
pp. 440-443

A new test generation method for sequential circuits (PDF)

D.H. Lee , Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Iowa Univ., Iowa City, IA, USA
pp. 446-449

Test generation for synchronous sequential circuits based on fault extraction (PDF)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 450-453

Increasing fault coverage for synchronous sequential circuits by the multiple observation time test strategy (PDF)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
L.N. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 454-457

A signal-driven discrete relaxation technique for architectural level test generation (PDF)

J. Lee , Center for Reliable High-Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel , Center for Reliable High-Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 458-461

Extended BDD's: trading off canonicity for structure in verification algorithms (PDF)

S.-W. Jeong , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
B. Plessier , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
G. Hachtel , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
F. Somenzi , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 464-467

Probabilistic design verification (PDF)

J. Jain , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
J. Bitner , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
D.S. Fussell , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
J.A. Abraham , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 468-471

Variable ordering and selection of FSM traversal (PDF)

S.-W. Jeong , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
B. Plessier , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
G.D. Hachtel , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
F. Somenzi , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 476-479

A convex optimization approach to transistor sizing for CMOS circuits (PDF)

S.S. Sapatnekar , Illinois Univ., Urbana, IL, USA
V.B. Rao , Illinois Univ., Urbana, IL, USA
P.M. Vaidya , Illinois Univ., Urbana, IL, USA
pp. 482-485

A new linear placement algorithm for cell generation (PDF)

E. Auer , Inst. of Electron. Design Automat., Tech. Univ. of Munich, Germany
pp. 486-489

A systematic approach for designing testable VLSI circuits (PDF)

S.-P. Lin , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
C.A. Njinda , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
M.A. Breuer , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 496-499

Design for easily applying test vectors to improve delay fault coverage (PDF)

E.H.-M. Sha , Dept. of Comput. Sci., Princeton Univ., NJ, USA
L.-F. Chao , Dept. of Comput. Sci., Princeton Univ., NJ, USA
pp. 500-503

The impedance fault model and design for robust impedance fault testability (PDF)

M.D. Sloan , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
W.A. Rogers , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
S. Shoroff , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 504-507

Application of Boolean unification to combinational logic synthesis (PDF)

M. Fujita , Fujitsu Laboratories Ltd., Kawasaki, Japan
Y. Tamiya , Fujitsu Laboratories Ltd., Kawasaki, Japan
pp. 510-513

Extracting local don't cares for network optimization (PDF)

H. Savoj , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 514-517

Observability relations and observability don't cares (PDF)

H. Savoj , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 518-521

Minimizing channel density by shifting blocks and terminals (PDF)

Y. Cai , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 524-527

The crossing distribution problem (PDF)

M. Marek-Sadowska , ECE Dept., California Univ., Santa Barbara, CA, USA
pp. 528-531

On topological via minimization and routing (PDF)

M. Hossain , Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
N.A. Sherwani , Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
pp. 532-535

Switchbox Steiner tree problem in presence of obstacles (PDF)

S. Miriyala , Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
J. Hashmi , Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
N. Sherwani , Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
pp. 536-539

PARIS: a parallel pattern fault simulator for synchronous sequential circuits (PDF)

N. Gouders , Dept. of Data Process., Duisburg Univ., Germany
pp. 542-545

Methods for reducing events in sequential circuit fault simulation (PDF)

E.M. Rudnick , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 546-549

A switch-level matrix approach to transistor-level fault simulation (PDF)

T. Lee , Illinois Univ., Urbana, IL, USA
I.N. Hajj , Illinois Univ., Urbana, IL, USA
pp. 554-557

Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs (PDF)

M. Fujita , Fujitsu Laboratories Ltd., Kawasaki, Japan
Y. Matsunaga , Fujitsu Laboratories Ltd., Kawasaki, Japan
pp. 560-563

Improved logic synthesis algorithms for table look up architectures (PDF)

R. Murgai , Dept. of EECS, California Univ., Berkeley, CA, USA
N. Shenoy , Dept. of EECS, California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of EECS, California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of EECS, California Univ., Berkeley, CA, USA
pp. 564-567

Technology mapping of lookup table-based FPGAs for performance (PDF)

R.J. Francis , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
J. Rose , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
Z. Vranesic , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
pp. 568-571

Performance directed synthesis for table look up programmable gate arrays (PDF)

R. Murgai , Dept. of EECS, California Univ., Berkeley, CA, USA
N. Shenoy , Dept. of EECS, California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of EECS, California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of EECS, California Univ., Berkeley, CA, USA
pp. 572-575
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