The Community for Technology Leaders
1989 IEEE International Conference on Computer-Aided Design (1989)
Santa Clara, CA, USA
Nov. 5, 1989 to Nov. 9, 1989
ISBN: 0-8186-1986-4
TABLE OF CONTENTS

Fast test generation for sequential circuits (PDF)

T.P. Kelsey , AT&T Bell Lab., Naperville, IL, USA
pp. 345-347

A powerful global router: based on Steiner min-max trees (PDF)

C. Chiang , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
M. Sarrafzadeh , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
pp. 2-5

A minimum separation algorithm for river routing with bounded number of jogs (PDF)

A. Mirzaian , Dept. of Comput. Sci., York Univ., North York, Ont., Canada
pp. 10-13

Module assignment and interconnect sharing in register-transfer synthesis of pipelined data paths (PDF)

N. Park , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
F.J. Kurdahi , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
pp. 16-19

A new integer linear programming formulation for the scheduling problem in data path synthesis (PDF)

Jiahn-Hung Lee , Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
Yu-Chin Hsu , Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
Youn-Long Lin , Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
pp. 20-23

Scheduling and hardware sharing in pipelined data paths (PDF)

K.S. Hwang , General Electric Corp., Schenectady, NY, USA
A.E. Casavant , General Electric Corp., Schenectady, NY, USA
C.-T. Chang , General Electric Corp., Schenectady, NY, USA
M.A. d'Abreu , General Electric Corp., Schenectady, NY, USA
pp. 24-27

Automating the diagnosis and the rectification of design errors with PRIAM (PDF)

J.C. Madre , BULL Corp. Res. Center, Louveciennes, France
O. Coudert , BULL Corp. Res. Center, Louveciennes, France
J.P. Billon , BULL Corp. Res. Center, Louveciennes, France
pp. 30-33

Accurate logic simulation in the presence of unknowns (PDF)

S.J. Chandra , CrossCheck Technol., San Jose, CA, USA
pp. 34-37

Restricted symbolic evaluation is fast and useful (PDF)

J.L. Carter , IBM Res. Div., Yorktown Heights, NY, USA
B.K. Rosen , IBM Res. Div., Yorktown Heights, NY, USA
pp. 38-41

CRACKER: a general area router based on stepwise reshaping (PDF)

S.H. Gerez , Fac. of Electr. Eng., Twente Univ., Enschede, Netherlands
O.E. Herrmann , Fac. of Electr. Eng., Twente Univ., Enschede, Netherlands
pp. 44-47

AGAR: a single-layer router for gate array cell generation (PDF)

M.A. Mostow , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 48-51

A new approach to sea-of-gates global routing (PDF)

T.-M. Parng , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.-S. Tsay , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 52-55

Manual rescheduling and incremental repair of register-level datapaths (PDF)

D.W. Knapp , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 58-61

A resource sharing and control synthesis method for conditional branches (PDF)

K. Wakabayashi , NEC Corp., Kawasaki, Japan
T. Yoshimura , NEC Corp., Kawasaki, Japan
pp. 62-65

A logic synthesis system for VHDL design descriptions (PDF)

T.E. Dillinger , IBM Application Bus. Syst., Rochester, MN, USA
K.M. McCarthy , IBM Application Bus. Syst., Rochester, MN, USA
T.A. Mosher , IBM Application Bus. Syst., Rochester, MN, USA
D.R. Neumann , IBM Application Bus. Syst., Rochester, MN, USA
R.A. Schmidt , IBM Application Bus. Syst., Rochester, MN, USA
pp. 66-69

A timing model for static CMOS gates (PDF)

H.-Y. Chen , Texas Instrum. Inc., Dallas, TX, USA
S. Dutta , Texas Instrum. Inc., Dallas, TX, USA
pp. 72-75

An accurate timing model for fault simulation in MOS circuits (PDF)

S. Kim , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
P. Banerjee , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 76-79

Event-EMU: an event driven timing simulator for MOS VLSI circuits (PDF)

B.D. Ackland , AT&T Bell Lab., Holmdel, NJ, USA
R.A. Clark , AT&T Bell Lab., Holmdel, NJ, USA
pp. 80-83

Automatic mixed-mode timing simulation (PDF)

D. Overhauser , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
I. Hajj , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Y.-F. Hsu , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 84-87

Global refinement for building block layout (PDF)

Yin-Meng Li , Dept. of Electron. Eng., Fudan Univ., Shanghai, China
Pu-Shan Tang , Dept. of Electron. Eng., Fudan Univ., Shanghai, China
pp. 90-93

Timing driven placement (PDF)

M. Marek-Sadowska , Electron. Res. Lab., California Univ., Berkeley, CA, USA
S.P. Lin , Electron. Res. Lab., California Univ., Berkeley, CA, USA
pp. 94-97

Combining partitioning and global routing in sea-of-cells design (PDF)

B. Korte , Forschungsinst. Fuer Diskrete Math., Bonn, West Germany
H.J. Promel , Forschungsinst. Fuer Diskrete Math., Bonn, West Germany
A. Steger , Forschungsinst. Fuer Diskrete Math., Bonn, West Germany
pp. 98-101

Layout methods for digital optical computing (PDF)

M. Murdocca , Dept. of Comput. Sci., Rutgers Univ., New Brunswick, NJ, USA
pp. 102-105

Tree-height minimization in pipelined architectures (PDF)

R. Hartley , General Electric Res. & Dev. Center, Schenectady, NY, USA
A. Casavant , General Electric Res. & Dev. Center, Schenectady, NY, USA
pp. 112-115

Synthesis of address generators (PDF)

D. Grant , Dept. of Electr. Eng., Edinburgh Univ., UK
P.B. Denyer , Dept. of Electr. Eng., Edinburgh Univ., UK
I. Finlay , Dept. of Electr. Eng., Edinburgh Univ., UK
pp. 116-119

Timing models in VAL/VHDL (PDF)

L.M. Augustin , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 122-125

On the computation of the ranges of detected delay fault sizes (PDF)

A.K. Pramanick , Dept. of Electr. & Comput. Eng., Iowa Univ., IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., IA, USA
pp. 126-129

A bounded delay race model (PDF)

C.-J. Seger , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 130-133

Two-dimensional compaction for placement refinement (PDF)

X.-M. Xiong , Appl. Micro Circuits Corp., San Diego, CA, USA
pp. 136-139

A custom cell generation system for double-metal CMOS technology (PDF)

P. Gee , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
I.N. Hajj , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
S.M. Kang , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 140-143

An O(n log n) algorithm for 1-D tile compaction (PDF)

R. Anderson , Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
S. Kahan , Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
pp. 144-147

An efficient algorithm for layout compaction problem with symmetry constraints (PDF)

R. Okuda , Dept. of Electron., Kyoto Univ., Japan
T. Sato , Dept. of Electron., Kyoto Univ., Japan
H. Onodera , Dept. of Electron., Kyoto Univ., Japan
K. Tamariu , Dept. of Electron., Kyoto Univ., Japan
pp. 148-151

Layout-driven test generation (PDF)

P. Nigh , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Maly , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 154-157

Optimal granularity of test generation in a distributed system (PDF)

H. Fujiwara , Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
T. Inoue , Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
pp. 158-161

The critical path for multiple faults (PDF)

S. Makar , Center for Reliable Comput., Stanford Univ., CA, USA
E. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 162-165

High performance test generation for accurate defect models in CMOS gate array technology (PDF)

H. Sucar , CrossCheck Technol. Inc., San Jose, CA, USA
S.J. Chandra , CrossCheck Technol. Inc., San Jose, CA, USA
D.J. Wharton , CrossCheck Technol. Inc., San Jose, CA, USA
pp. 166-169

Mixed-mode simulation of compiled VHDL programs (PDF)

R.D. Acosta , Microelectron. & Comput. Technol. Corp., Austin, TX, USA
S.P. Smith , Microelectron. & Comput. Technol. Corp., Austin, TX, USA
J. Larson , Microelectron. & Comput. Technol. Corp., Austin, TX, USA
pp. 176-179

Switch-level VHDL descriptions (PDF)

A.G. Stanculescu , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 180-183

An efficient method for parametric yield optimization of MOS integrated circuits (PDF)

T.K. Yu , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
S.M. Kang , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 190-193

A new methodology for the design centering of IC fabrication processes (PDF)

K.K. Low , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
S.W. Director , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 194-197

Statistical bipolar circuit design using MSTAT (PDF)

N. Salamina , Motorola Inc., Tempe, AZ, USA
M.R. Rencher , Motorola Inc., Tempe, AZ, USA
pp. 198-201

Computation of bus current variance for reliability estimation of VLSI circuits (PDF)

F. Najm , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
I. Hajj , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 202-205

Boolean minimization and algebraic factorization procedures for fully testable sequential machines (PDF)

S. Devadas , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 208-211

State assignment for initializable synthesis (gate level analysis) (PDF)

K.-T. Cheng , AT&T Bell Lab., Murray Hill, NJ, USA
V.D. Agrawal , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 212-215

Optimum and heuristic algorithms for finite state machine decomposition and partitioning (PDF)

P. Ashar , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
S. Devadas , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A.R. Newton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 216-219

State assignment for multilevel logic using dynamic literal estimation (PDF)

M. Bolotski , Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
D. Camporese , Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
R. Barman , Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
pp. 220-223

A novel reconfiguration scheme for 2-D processor arrays (PDF)

P.K. Rhee , Center for Adv. Comput. Studies, Southwest Louisiana Univ., Lafayette, LA, USA
J.H. Kim , Center for Adv. Comput. Studies, Southwest Louisiana Univ., Lafayette, LA, USA
pp. 230-233

Fault detection and location in reconfigurable VLSI arrays (PDF)

K. Wang , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
S.-Y. Kuo , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
pp. 234-237

Optimal wafer probe testing and diagnosis of k-out-of-n structures (PDF)

M.-F. Chang , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
W. Shi , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
W.K. Fuchs , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 238-241

A table look-up model using a 3-D isoparametric shape function with improved convergency (PDF)

Dae-Hyung Cho , Samsung Electron. Semicond. Bus., Kyung Ki-Do, South Korea
Tae-Han Kim , Samsung Electron. Semicond. Bus., Kyung Ki-Do, South Korea
Jeong-Taek Kong , Samsung Electron. Semicond. Bus., Kyung Ki-Do, South Korea
pp. 244-247

Piecewise approximate circuit simulation (PDF)

C. Visweswariah , Carnegie Mellon Univ., Pittsburgh, PA, USA
R.A. Rohrer , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 248-251

SPECS simulation validation with efficient transient sensitivity computation (PDF)

T.V. Nguyen , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
P. Feldmann , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
S.W. Director , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.A. Rohrer , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 252-255

Thermal analysis in SPICE (PDF)

R.P. Pokala , Valid Logic Syst., San Jose, CA, USA
D. Divekar , Valid Logic Syst., San Jose, CA, USA
pp. 256-259

Translating concurrent programs into delay-insensitive circuits (PDF)

E. Brunvand , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 262-265

Practicality of state-machine verification of speed-independent circuits (PDF)

S.M. Nowick , Comput. Syst. Lab., Stanford Univ., CA, USA
D.L. Dill , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 266-269

Inserting active delay elements to achieve wave pipelining (PDF)

D. Wong , Dept. of Electr. Eng., Stanford Univ., CA, USA
G. De Micheli , Dept. of Electr. Eng., Stanford Univ., CA, USA
M. Flynn , Dept. of Electr. Eng., Stanford Univ., CA, USA
pp. 270-273

A data model and architecture for VLSI/CAD databases (PDF)

A. Singhal , AT&T Bell Lab., Murray Hill, NJ, USA
N. Parikh , AT&T Bell Lab., Murray Hill, NJ, USA
D. Dutt , AT&T Bell Lab., Murray Hill, NJ, USA
C.-Y. Lo , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 276-279

SLIP: a software environment for system level interactive partitioning (PDF)

M. Beardslee , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
C. Kring , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R. Murgai , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
H. Savoj , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A.R. Newton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 280-283

Optimal layout via Boolean satisfiability (PDF)

S. Devadas , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 294-297

Towards efficient hierarchical designs by ratio cut partitioning (PDF)

Yen-Chuen Wei , Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
Chung-Kuan Cheng , Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
pp. 298-301

Pin assignment with global routing (PDF)

J. Cong , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 302-305

On optimal extraction of combinational logic and don't care sets from hardware description languages (PDF)

G. Colon-Bonet , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
E.M. Schwarz , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
D.G. Bostick , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
G.D. Hachtel , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
M.R. Lightner , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 308-311

PLA decomposition with generalized decoders (PDF)

S. Yang , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
M.J. Ciesielski , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 312-315

An exact minimizer for Boolean relations (PDF)

R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 316-319

WireLisp: combining graphics and procedures in a circuit specification language (PDF)

C. Ebeling , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
Z. Wu , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 322-325

Fast incremental netlist compilation of hierarchical schematics (PDF)

L.G. Jones , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 326-329

Structure optimization in logic schematic generation (PDF)

T.D. Lee , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
L.P. McNamee , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 330-333

A new approach to optimal cell synthesis (PDF)

J. Madsen , DesignCenter of Electron. Inst., Tech. Univ. of Denmark, Lyngby, Denmark
pp. 336-339

CLEO: a CMOS layout generator (PDF)

A. Domic , Digital Equipment Corp., Hudson, MA, USA
S. Levitin , Digital Equipment Corp., Hudson, MA, USA
N. Phillips , Digital Equipment Corp., Hudson, MA, USA
C. Thai , Digital Equipment Corp., Hudson, MA, USA
T. Shiple , Digital Equipment Corp., Hudson, MA, USA
D. Bhavsar , Digital Equipment Corp., Hudson, MA, USA
C. Bissel , Digital Equipment Corp., Hudson, MA, USA
pp. 340-343

An optimal transistor-chaining algorithm for CMOS cell layout (PDF)

Chi-Yi Hwang , Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
Yung-Ching Hsieh , Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
Youn-Long Lin , Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
Yu-Chin Hsu , Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
pp. 344-347

CETUS-a versatile custom cell synthesizer (PDF)

P.K. Sun , Control Data Corp., Minneapolis, MN, USA
pp. 348-351

Design of sequential machines for efficient test generation (PDF)

K.-T. Cheng , AT&T Bell Lab., Murray Hill, NJ, USA
V.D. Agrawal , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 358-361

Test generation for highly sequential circuits (PDF)

A. Ghosh , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
S. Devadas , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A.R. Newton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 362-365

FACT-a testability analysis methodology (PDF)

T. Sridhar , Gateway Design Autom. Corp., Lowell, MA, USA
pp. 366-369

A manufacturing-oriented environment for synthesis of fabrication processes (PDF)

J.S. Wenstrand , Center for Integrated Syst., Stanford Univ., CA, USA
pp. 376-379

Yoda: a framework for the conceptual design VLSI systems (PDF)

A.M. Dewey , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
S.W. Director , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 380-383

The EVE VLSI information management environment (PDF)

H. Afsarmanesh , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
E. Brotoatmodjo , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
K.J. Byeon , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
A.C. Parker , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 384-387

Interconnection length estimation for optimized standard cell layouts (PDF)

M. Pedram , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 390-393

Early matching of system requirements and package capabilities (PDF)

D.P. LaPotin , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Y.-H. Chen , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 394-397

A clock distribution scheme for nonsymmetric VLSI circuits (PDF)

P. Ramanathan , Dept. of Electron. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
K.G. Shin , Dept. of Electron. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 398-401

A Newton waveform relaxation algorithm for circuit simulation (PDF)

D.J. Erdman , Duke Univ., Durham, NC, USA
D.J. Rose , Duke Univ., Durham, NC, USA
pp. 404-407

PGS and PLUCGS-two new matrix solution techniques for general circuit simulation (PDF)

R. Burch , Texas Instrum., Dallas, TX, USA
K. Mayaram , Texas Instrum., Dallas, TX, USA
J.-H. Chern , Texas Instrum., Dallas, TX, USA
P. Yang , Texas Instrum., Dallas, TX, USA
P. Cox , Texas Instrum., Dallas, TX, USA
pp. 408-411

Waveform relaxation for transient simulation of two-dimensional MOS devices (PDF)

M. Reichelt , Res. Lab. of Electron., MIT, Cambridge, MA, USA
J. White , Res. Lab. of Electron., MIT, Cambridge, MA, USA
J. Allen , Res. Lab. of Electron., MIT, Cambridge, MA, USA
pp. 412-415

Synthesis of delay fault testable combinational logic (PDF)

K. Roy , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 418-421

Consistency and observability invariance in multi-level logic synthesis (PDF)

P. McGeer , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 426-429

An efficient channel routing algorithm for defective arrays (PDF)

H.Y. Youn , Dept. of Comput. Sci., North Texas Univ., Denton, TX, USA
pp. 432-435

Routing using a pyramid data structure (PDF)

Youn-Long Lin , Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
Yu-Chin Hsu , Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
Fur-Shing Tsai , Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
pp. 436-439

HAM-a hardware accelerator for multi-layer wire routing (PDF)

R. Venkateswaran , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
P. Mazumder , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 440-443

LADIES: an automatic layout system for analog LSI's (PDF)

M. Mogaki , Hitachi Ltd., Tokyo, Japan
N. Kato , Hitachi Ltd., Tokyo, Japan
Y. Chikami , Hitachi Ltd., Tokyo, Japan
N. Yamada , Hitachi Ltd., Tokyo, Japan
Y. Kobayashi , Hitachi Ltd., Tokyo, Japan
pp. 450-453

Functional comparison of logic designs for VLSI circuits (PDF)

C.L. Berman , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
L.H. Trevillyan , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 456-459

Specification and verification of VLSI systems (PDF)

A. Wilk , Dept. of Comput. Sci., Weizmann Inst. of Sci., Rehovot, Israel
A. Pnueli , Dept. of Comput. Sci., Weizmann Inst. of Sci., Rehovot, Israel
pp. 460-463

FANHAT: fanout oriented hierarchical automatic test generation system (PDF)

H.B. Min , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
W.A. Rogers , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
H.-T.A. Luh , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 470-473

High-speed compiled-code simulation of transition faults (PDF)

M. Geilert , Inst. fuer Theor. Elektrotech., Hannover Univ., West Germany
pp. 478-481

An algorithm for hierarchical floorplan design (PDF)

D.F. Wong , Dept. of Comput. Sci., Texas Univ., TX, USA
K.-S. The , Dept. of Comput. Sci., Texas Univ., TX, USA
pp. 484-487

Constrained floorplan design for flexible blocks (PDF)

S.-K. Dong , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
J. Cong , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
C.L. Liu , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 488-491

Multi-terrain partitioning and floor-planning for data-path chip (microprocessor) layout (PDF)

W.K. Luk , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 492-495

Hierarchical compiled event-driven logic simulation (PDF)

D.M. Lewis , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
pp. 498-501

A model for comparing synchronization strategies for parallel logic-level simulation (PDF)

M.L. Bailey , Dept. of Comput. Sci., Arizona Univ., Tucson, AZ, USA
pp. 502-505

Portable parallel logic and fault simulation (PDF)

R.B. Mueller-Thuns , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
D.G. Saab , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 506-509

Modeling uncertainty in RC timing analysis (PDF)

C.L. Harkness , Dept. of Comput. Sci., Brown Univ., Providence, RI, USA
D.P. Lopresti , Dept. of Comput. Sci., Brown Univ., Providence, RI, USA
pp. 516-519

Critical path issue in VLSI design (PDF)

H. Youssef , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
E. Shragowitz , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
L. Bening , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 520-523

PACE2: an improved parallel VLSI extractor with parameter extraction (PDF)

K.P. Belkhale , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
P. Banerjee , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 526-529

C3DSTAR: a 3D wiring capacitance calculator (PDF)

J.F. Janak , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
D.D. Ling , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 530-533

The Stickizer: a layout to symbolic converter (PDF)

J.-C. Dufourd , CNET, Meylan, France
pp. 534-537

A layout defect-sensitivity extractor (PDF)

J.P. de Gyvez , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
J.A.G. Jess , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
pp. 538-541

Fast two-level logic minimizers for multi-level logic synthesis (PDF)

H. Savoj , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A.A. Malik , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 544-547

New ATPG techniques for logic optimization (PDF)

R. Jacoby , Colorado Univ., Boulder, CO, USA
P. Moceyunas , Colorado Univ., Boulder, CO, USA
H. Cho , Colorado Univ., Boulder, CO, USA
G. Hachtel , Colorado Univ., Boulder, CO, USA
pp. 548-551

SYLON-DREAM: a multi-level network synthesizer (PDF)

K.-C. Chen , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
S. Muroga , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 552-555

Multi-level logic optimization using binary decision diagrams (PDF)

Y. Matsunaga , Fujitsu Lab. Ltd., Kawasaki, Japan
M. Fujita , Fujitsu Lab. Ltd., Kawasaki, Japan
pp. 556-559

Fault detection in a testable PLA with low overhead for production testing (PDF)

Y.-N. Shen , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
F. Lombardi , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 566-569

Arithmetic and galois checksums (PDF)

N.R. Saxena , Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 570-573

A diagnosis method using pseudo-random vectors without intermediate signatures (PDF)

R.C. Aitken , VLSI Design Lab., McGill Univ., Montreal, Que., Canada
V.K. Agarwal , VLSI Design Lab., McGill Univ., Montreal, Que., Canada
pp. 574-577
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