The Community for Technology Leaders
1988 IEEE International Conference on Computer-Aided Design (1988)
Santa Clara, CA, USA
Nov. 7, 1988 to Nov. 10, 1988
ISBN: 0-8186-0869-2
TABLE OF CONTENTS

Evaluation and improvement of Boolean comparison method based on binary decision diagrams (PDF)

M. Fujita , Fujitsu Lab. Ltd., Kawasaki, Japan
H. Fujisawa , Fujitsu Lab. Ltd., Kawasaki, Japan
N. Kawato , Fujitsu Lab. Ltd., Kawasaki, Japan
pp. 2-5

Logic verification using binary decision diagrams in a logic synthesis environment (PDF)

S. Malik , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A.R. Wang , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 6-9

BEATNP: a tool for partitioning Boolean networks (PDF)

H. Cho , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
G. Hachtel , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
M. Nash , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
L. Setiono , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 10-13

An efficient macromodeling approach for statistical IC process design (PDF)

K.K. Low , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
S.W. Director , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 16-19

iEDISON: an interactive statistical design tool for MOS VLSI circuits (PDF)

T.K. Yu , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
S.M. Kang , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
I.N. Hajj , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
T.N. Trick , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 20-23

An efficient method for circuit sensitivity calculation using piecewise linear waveform models (PDF)

S.M. Kang , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Y. Leblebici , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 24-27

Codar: a congestion-directed general area router (PDF)

Pin-San Tzeng , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
C.H. Sequin , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 30-33

Carioca-A 'smart' and flexible switch-box router (PDF)

P.-F. Dubois , CNET, CNS/CCI, Meylan, France
A. Puissochet , CNET, CNS/CCI, Meylan, France
A.-M. Tagant , CNET, CNS/CCI, Meylan, France
pp. 34-37

A detailed router based on simulated evolution (PDF)

Youn-Long Lin , Dept. of Comput. Sci., Tsing Hua Univ., Hsin-Chu, Taiwan
Yu-Chin Hsu , Dept. of Comput. Sci., Tsing Hua Univ., Hsin-Chu, Taiwan
Fur-Shing Tsai , Dept. of Comput. Sci., Tsing Hua Univ., Hsin-Chu, Taiwan
pp. 38-41

Automatic synthesis of a multi-bus architecture for DSP (PDF)

B.S. Haroun , Dept. of Electr. Eng., Waterloo Univ., Ont., Canada
M.I. Elmasry , Dept. of Electr. Eng., Waterloo Univ., Ont., Canada
pp. 44-47

Area-time model for synthesis of non-pipelined designs (PDF)

R. Jain , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
M.J. Mlinar , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
A. Parker , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 48-51

Constrained conditional resource sharing in pipeline synthesis (PDF)

Ki Soo Hwang , Gen. Electr. Corp. Res. & Dev., Schenectady, NY, USA
A.E. Casavant , Gen. Electr. Corp. Res. & Dev., Schenectady, NY, USA
M. Dragomirecky , Gen. Electr. Corp. Res. & Dev., Schenectady, NY, USA
M.A. d'Abreu , Gen. Electr. Corp. Res. & Dev., Schenectady, NY, USA
pp. 52-55

Combining event and data-flow graphs in behavioral synthesis (PDF)

G. Borriello , Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
pp. 56-59

Bisim: a simulator for custom ECL circuits (PDF)

R. Kao , Comput. Syst. Lab., Stanford Univ., CA, USA
B. Alverson , Comput. Syst. Lab., Stanford Univ., CA, USA
M. Horowitz , Comput. Syst. Lab., Stanford Univ., CA, USA
D. Stark , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 62-65

XPSim: a MOS VLSI simulator (PDF)

R.L. Bauer , Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Jiayuan Fang , Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A.P.-C. Ng , Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 66-69

A tabular macromodeling approach to fast timing simulation including parasitics (PDF)

D. Overhauser , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
I. Hajj , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 70-73

Over-the-cell channel routing (PDF)

Jingsheng Cong , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
C.L. Liu , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 80-83

Net characterization based channel router: FT router (PDF)

H. Zhu , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
R.H. Fujii , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 84-87

MulCh: a multi-layer channel router using one, two, and three layer partitions (PDF)

R.I. Greenberg , Lat. for Comput. Sci., MIT, Cambridge, MA, USA
A.T. Ishii , Lat. for Comput. Sci., MIT, Cambridge, MA, USA
pp. 88-91

Performance enhancements in BOLD using 'implications' (PDF)

G. Hachtel , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
R. Jacoby , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
P. Moceyunas , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
C. Morrison , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 94-97

Don't cares and global flow analysis of Boolean networks (PDF)

R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
E.M. Sentovich , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 98-101

Improved logic optimization using global flow analysis (PDF)

L. Berman , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
L. Trevillyan , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 102-105

A modified approach to two-level logic minimization (PDF)

A.A. Malik , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A.R. Newton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A.L. Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 106-109

CODECS: a fixed mixed-level device and circuit simulator (PDF)

K. Mayaram , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
D.O. Pederson , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 112-115

A grid generation system for process and device simulation (PDF)

A. Yajima , Hitachi Ltd., Tokyo, Japan
H. Jonishi , Hitachi Ltd., Tokyo, Japan
A. Maruyama , Hitachi Ltd., Tokyo, Japan
pp. 116-119

A submicron MOSFET model for simulation of analog circuits (PDF)

A. Chatterjee , Texas Instrum. Inc., Dallas, TX, USA
C.F. Machala , Texas Instrum. Inc., Dallas, TX, USA
Ping Yang , Texas Instrum. Inc., Dallas, TX, USA
pp. 120-123

A table look-up MOSFET model for analog applications (PDF)

P.E. Allen , Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
K.S. Yoon , Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 124-127

Gate matrix partitioning (PDF)

Shuo Huang , Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
O. Wing , Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
pp. 130-133

Doubly folded transistor matrix layout (PDF)

L.P.P.P. van Genneken , Design Autom. Sect., Eindhoven Univ. of Technol., Netherlands
J.T.J. van Eijndhoven , Design Autom. Sect., Eindhoven Univ. of Technol., Netherlands
J.A.H.C.M. Brouwers , Design Autom. Sect., Eindhoven Univ. of Technol., Netherlands
pp. 134-137

A new algorithm for CMOS gate matrix layout (PDF)

C.Y.R. Chen , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
C.Y. Hou , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
pp. 138-141

CLAY: a malleable-cell multi-cell transistor matrix approach for CMOS LAYout synthesis (PDF)

P. Kollaritsch , Texas Instrum., Dallas, TX, USA
S. Lusky , Texas Instrum., Dallas, TX, USA
S. Prasad , Texas Instrum., Dallas, TX, USA
N. Potter , Texas Instrum., Dallas, TX, USA
pp. 142-145

Decomposition and factorization of sequential finite state machines (PDF)

S. Devadas , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 148-151

A fast algorithm for the optimal state assignment of large finite state machines (PDF)

D. Varma , Electr. Comput. Eng. Dept., Drexel Univ., Philadelphia, PA, USA
E.A. Trachtenberg , Electr. Comput. Eng. Dept., Drexel Univ., Philadelphia, PA, USA
pp. 152-155

A new method for the efficient state-assignment of PLA-based sequential machines (PDF)

J.L. Huertas , Dept. of Electron. y Electromagn., Univ. de Sevilla, Spain
J.M. Quintana , Dept. of Electron. y Electromagn., Univ. de Sevilla, Spain
pp. 156-159

Critical path tracing in sequential circuits (PDF)

P.R. Menon , Massachusetts Univ., Amherst, MA, USA
pp. 162-165

A fast fault simulation algorithm for combinational circuits (PDF)

Wuudiann Ke , Dept. of Comput. Sci., Nebraska Univ., Lincoln, NE, USA
S. Seth , Dept. of Comput. Sci., Nebraska Univ., Lincoln, NE, USA
pp. 166-169

A fault simulation method based on stem regions (PDF)

F. Maamari , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
J. Rajski , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 170-173

A new algorithm for standard cell global routing (PDF)

Jinepheng Cong , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 176-179

A new global router for row-based layout (PDF)

K.-W. Lee , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
C. Sechen , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
pp. 180-183

Channel routing order for building-block layout with rectilinear modules (PDF)

M. Guruswamy , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 184-187

Parallel logic/fault simulation of VLSI array logic (PDF)

P. Bose , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 190-193

Parallel PLA fault simulation based on Boolean vector operations (PDF)

E. Chiprout , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
J. Rajski , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
M. Robinson , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 194-197

Vectorized fault simulation on the Cray X-MP supercomputer (PDF)

F. Ozguner , Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA
R. Daoud , Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA
pp. 198-201

CREST-a current estimator for CMOS circuits (PDF)

F. Najm , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 204-207

Time domain current waveform simulation of CMOS circuits (PDF)

An-Chang Deng , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Yan-Chyuan Shiau , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
K.-H. Loh , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 208-211

Current estimation in MOS IC logic circuits (PDF)

S. Chowdhury , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
J.S. Barkatullah , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 212-215

Combining circuit level changes with electrical optimization (PDF)

F.W. Obermeier , Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.H. Katz , Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 218-221

A method for net representation with polygon decomposition (PDF)

C.-P.G. Chi , Siemens Transmission Syst. Inc., Phoenix, AZ, USA
pp. 222-225

NOISY: an electrical noise checker for ULSI (PDF)

F. Gourdy , Bull Syst., Clayes Sous Bois, France
A. Greiner , Bull Syst., Clayes Sous Bois, France
M. Guillemet , Bull Syst., Clayes Sous Bois, France
R. Marbot , Bull Syst., Clayes Sous Bois, France
J. Murzin , Bull Syst., Clayes Sous Bois, France
pp. 226-229

Aliasing probability of non-exhaustive randomized syndrome tests (PDF)

R.C. Aitken , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
V.K. Agarwal , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 232-235

Built-in self-test for large embedded CMOS folded PLAs (PDF)

R. Dandapani , Dept. of Electr. Eng., Colorado Univ., Colorado Springs, CO, USA
pp. 236-239

On the design of robust multiple fault testable CMOS combinational logic circuits (PDF)

S. Kundu , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 240-243

CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits (PDF)

D.G. Saab , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
R.B. Mueller-Thuns , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
D. Blaauw , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
J.A. Abraham , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 246-249

M/sup 3/-a multilevel mixed-mode mixed D/A simulator (PDF)

R. Chadha , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 258-261

Modeling and enhancing virtual memory performance in logic simulation (PDF)

S.P. Smith , Microelectron. & Comput. Technol. Corp., Austin, TX, USA
J. Kuban , Microelectron. & Comput. Technol. Corp., Austin, TX, USA
pp. 264-267

Logic simulation on vector processors (PDF)

R. Raghavan , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
J.P. Hayes , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
W.R. Martin , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 268-271

Discrete-event simulation on hypercube architectures (PDF)

R.D. Chamberlain , Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA
M.A. Franklin , Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA
pp. 272-275

Parallel polygon operations using loosely coupled workstations (PDF)

R. Widdowson , Dept. of Comput. Sci., Edinburgh Univ., UK
pp. 276-279

Timing optimization of combinational logic (PDF)

K.J. Singh , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A.R. Wang , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 282-285

Experiments in logic optimization (PDF)

M. Lightner , Colorado Univ., Boulder, CO, USA
pp. 286-289

Boolean decomposition in multi-level logic optimization (PDF)

S. Devadas , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 290-293

Hill climbing with reduced search space (logic optimization) (PDF)

D. Brand , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 294-297

Partitioning issues in circuit simulation on multiprocessors (PDF)

D.C. Yeh , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
V.B. Rao , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 300-303

iPRIDE: a parallel integrated circuit simulator using direct method (PDF)

Mi-Chang Chang , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
I.N. Hajj , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 304-307

A band relaxation algorithm for reliable and parallelizable circuit simulation (PDF)

A. Lumsdaine , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
J. White , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 308-311

Taking advantage of optimal on-chip parallelism for parallel discrete-event simulation (PDF)

J.V. Briner , Dept. of Comput. Sci., Duke Univ., Durham, NC, USA
J.L. Ellis , Dept. of Comput. Sci., Duke Univ., Durham, NC, USA
G. Kedem , Dept. of Comput. Sci., Duke Univ., Durham, NC, USA
pp. 312-315

Stick diagram extraction program SKELETON (PDF)

M. Sato , Toshiba Corp., Kawasaki, Japan
pp. 318-321

GeminiII: a second generation layout validation program (PDF)

C. Ebeling , Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
pp. 322-325

PACE: a parallel VLSI extractor on the Intel hypercube multiprocessor (PDF)

K.P. Belkhale , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
P. Banerjee , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 326-329

Predictive subset testing for IC performance (PDF)

J.B. Brockman , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
S.W. Director , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 336-339

Built-in current testing-feasibility study (PDF)

W. Maly , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
P. Nigh , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 340-343

Testing oriented analysis of CMOS ICs with opens (PDF)

W. Maly , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
P.K. Nag , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
P. Nigh , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 344-347

Data parallel switch-level simulation (PDF)

R.E. Bryant , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 354-357

Delay computation in switch-level models of non-treelike MOS circuits (PDF)

D. Martin , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
N.C. Rumin , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 358-361

Optimal CMOS cell transistor placement: a relaxation approach (PDF)

A. Stauffer , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R. Nair , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 364-367

A new layout optimization methodology for CMOS complex gates (PDF)

C.Y.R. Chen , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
C.Y. Hou , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
pp. 368-371

iCOACH: a circuit optimization aid for CMOS high-performance circuits (PDF)

H.Y. Chen , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
S.M. Kang , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 372-375

Compaction of ATPG-generated test sequences for sequential circuits (PDF)

R.K. Roy , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
T.M. Niermann , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
J.H. Patel , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
J.A. Abraham , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
R.A. Saleh , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 382-385

Efficient handling of large wiring data in TANGATE (PDF)

T. Kronmiller , Tangent Syst., Santa Clara, CA, USA
pp. 388-391

Cbase 1.0: a CAD database for VLSI circuits using object oriented technology (PDF)

M.A. Breuer , Univ. of Southern California, Los Angeles, CA, USA
W. Cheng , Univ. of Southern California, Los Angeles, CA, USA
R. Gupta , Univ. of Southern California, Los Angeles, CA, USA
I. Hardonag , Univ. of Southern California, Los Angeles, CA, USA
E. Horowitz , Univ. of Southern California, Los Angeles, CA, USA
S.Y. Lin , Univ. of Southern California, Los Angeles, CA, USA
pp. 392-395

Flexible module generation in the FACE design environment (PDF)

W.D. Smith , General Electric Corp. Res. & Dev., Schenectady, NY, USA
J.R. Jasica , General Electric Corp. Res. & Dev., Schenectady, NY, USA
M.J. Hartman , General Electric Corp. Res. & Dev., Schenectady, NY, USA
M.A. d'Abreu , General Electric Corp. Res. & Dev., Schenectady, NY, USA
pp. 396-399

A linear-time Steiner tree routing algorithm for terminals on the boundary of a rectangle (PDF)

J.P. Cohoon , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
D.S. Richards , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
J.S. Salowe , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 402-405

Topological channel routing (PDF)

S. Haruyama , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D. Fussell , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 406-409

A new algorithm for topological routing and via minimization (PDF)

Xiong Xiao-Ming , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 410-413

Automatic test generation using neural networks (PDF)

S.T. Chakradhar , Dept. of Comput. Sci., Rutgers Univ., New Brunswick, NJ, USA
pp. 416-419

A tool for hierarchical test generation (PDF)

G. Kruger , Nixdorf Comput. AG, Paderborn, West Germany
pp. 420-423

NCUBE: an automatic test generation program for iterative logic arrays (PDF)

A. Chatterjee , Illinois Univ., Urbana, IL, USA
J.A. Abraham , Illinois Univ., Urbana, IL, USA
pp. 428-431

A dormant subcircuit model for maximizing iteration latency (PDF)

P. Cox , Texas Instrum. Inc., Dallas, TX, USA
R. Burch , Texas Instrum. Inc., Dallas, TX, USA
P. Yang , Texas Instrum. Inc., Dallas, TX, USA
pp. 438-441

PYRAMID-a hierarchical waveform relaxation-based circuit simulation program (PDF)

P. Saviz , Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
O. Wing , Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
pp. 442-445

An envelope-following method for the efficient transient simulation of switching power and filter circuits (PDF)

K. Kundert , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
J. White , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
A. Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 446-449

Floorplan design using distributed genetic algorithms (PDF)

J.P. Cohoon , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
S.U. Hegde , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
W.N. Martin , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
D. Richards , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 452-455

Automatically extracting structure from a logical design (PDF)

M. Hirsch , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
D. Siewiorek , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 456-459

Hierarchical placement for macrocells: a 'meet in the middle' approach (PDF)

B. Eschermann , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Dai Wei-Ming , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
E.S. Kuh , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
M. Pedram , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 460-463

Automatic synthesis and technology mapping of combinational logic (PDF)

R.A. Bergamaschi , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
pp. 466-469

Technology mapping for standard-cell generators (PDF)

M.R.C.M. Berkelaar , Eindhoven Univ. of Technol., Netherlands
J.A.G. Jess , Eindhoven Univ. of Technol., Netherlands
pp. 470-473

Input assignment algorithm for decoded-PLAs with multi-input decoders (PDF)

Kuang-Chien Chen , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
S. Muroga , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 474-477

PLA optimization using output encoding (PDF)

A. Saldanha , Electr. Eng. & Comput. Sci. Dept., California Univ., Berkeley, CA, USA
R.H. Katz , Electr. Eng. & Comput. Sci. Dept., California Univ., Berkeley, CA, USA
pp. 478-481

ECSTASY: a new environment for IC design optimization (PDF)

Shyu Jyuo-Min , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 484-487

Analog circuit synthesis for performance in OASYS (PDF)

R. Harjani , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
R.A. Rutenbar , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
L.R. Carley , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 492-495

CLANS: a high-level synthesis tool for high resolution data converters (PDF)

J.G. Kenney , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
L.R. Carley , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 496-499

An improved objective function for mincut circuit partitioning (PDF)

C. Sechen , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
D. Chen , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
pp. 502-505

GORDIAN: a new global optimization/rectangle dissection method for cell placement (PDF)

J.M. Kleinhans , Dept. of Electr. Eng., Tech. Univ. of Munich, West Germany
G. Sigl , Dept. of Electr. Eng., Tech. Univ. of Munich, West Germany
F.M. Johannes , Dept. of Electr. Eng., Tech. Univ. of Munich, West Germany
pp. 506-509

Simulated annealing: a fast heuristic for some generic layout problems (PDF)

J. Lam , Yale Univ., New Haven, CT, USA
J.-M. Delosne , Yale Univ., New Haven, CT, USA
pp. 510-513

Temperature measurement of simulated annealing placements (PDF)

J. Rose , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 514-517

A new formulation of yield enhancement problems for reconfigurable chips (PDF)

N. Hasan , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
J. Cong , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
C.L. Liu , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 520-523

Diagnosis and repair of memory with coupling faults (PDF)

Chang Ming-Feng , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
W.K. Fuchs , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
J.H. Patel , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 524-527

Two-layer quad trees: a data structure for high-speed interactive layout tools (PDF)

Li Wanhao , Motorola Inc., Chandler, AZ, USA
S. Legendre , Motorola Inc., Chandler, AZ, USA
K. Gardiner , Motorola Inc., Chandler, AZ, USA
pp. 530-533

The use of inverse layout trees for hierarchical design verification (PDF)

N. Hedenstierna , Sch. of Electr. & Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
K.O. Jeppson , Sch. of Electr. & Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
pp. 534-537

Expanded rectangles: a new VLSI data structure (PDF)

M. Quayle , Dept. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
pp. 538-541

Automatic layout of custom analog cells in ANAGRAM (PDF)

D.J. Garrod , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
R.A. Rutenbar , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
L.R. Carley , Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 544-547

Automatic layout generation for CMOS operational amplifiers (PDF)

Koh Han Young , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
C.H. Sequin , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
P.R. Gray , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 548-551

Test generation for sequential circuits using individual initial value propagation (PDF)

T. Ogihara , Mitsubishi Electr. Corp., Kamakura, Japan
S. Saruyama , Mitsubishi Electr. Corp., Kamakura, Japan
S. Murai , Mitsubishi Electr. Corp., Kamakura, Japan
pp. 242-247
96 ms
(Ver 3.3 (11022016))