The Third Workshop on Future Trends of Distributed Computing Systems (1992)
April 14, 1992 to April 16, 1992
S. Nishimura , Dept. of Inf. Sci., Tokyo Univ., Hongo, Japan
R. Mukai , Dept. of Inf. Sci., Tokyo Univ., Hongo, Japan
T.L. Kunii , Dept. of Inf. Sci., Tokyo Univ., Hongo, Japan
This paper describes a parallel computer architecture for real-time image synthesis. The architecture is based on a loosely-coupled array of general purpose processors equipped with a novel frame buffer subsystem called a conflict-free multiport frame buffer (CFMFB) which enables every processor to write any region of the screen without access conflicts. An efficient polygon rendering method using the CFMFB is also described. The method assigns a subset of the polygons to each processor, which independently calculates the images of the assigned polygons with the Z-buffer algorithm. The performance of the system is estimated through simulation experiments with sample scenes.<
computer graphics, image processing, parallel architectures, performance evaluation
S. Nishimura, R. Mukai and T. Kunii, "A loosely-coupled parallel graphics architecture based on a conflict-free multiport frame buffer," The Third Workshop on Future Trends of Distributed Computing Systems(FTDCS), Taipei, Taiwan, , pp. 411-418.