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Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing (1994)
Austin, TX, USA
June 15, 1994 to June 17, 1994
ISBN: 0-8186-5520-8
pp: 48-54
L. Baldelli , Dipartimento di Inf., Pisa Univ., Italy
P. Maestrini , Dipartimento di Inf., Pisa Univ., Italy
ABSTRACT
This paper introduces an approach to diagnosis of processor arrays, assuming that processors are horizontally, vertically and diagonally connected to their neighbors. The proposed algorithm subdivides the array into clusters containing nine processors and requires three steps. In the first step each cluster executes tests according to a rosace pattern, and clusters for which all test results were zero are classified as Z-Cs. The remaining cluster, which contain at least one fault, are classified NZ-Cs. In the second step. Z-Cs are combined into aggregates (ZACS) and one Z-ACs is identified as a fault-free core of the array. The third step leads to identification of the state (of faulty or non faulty) of more nodes. The diagnosis is proved to be correct, although possibly incomplete, assuming that the number of faults is less that a bound T, which is an increasing function of the size of the array.<>
INDEX TERMS
logic arrays, multiprocessing systems, logic testing, sequential circuits, computer testing
CITATION

L. Baldelli and P. Maestrini, "Diagnosis of processor arrays," Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing(FTCS), Austin, TX, USA, 1994, pp. 48-54.
doi:10.1109/FTCS.1994.315658
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