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Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing (1994)
Austin, TX, USA
June 15, 1994 to June 17, 1994
ISBN: 0-8186-5520-8
pp: 76-85
M. Rimen , Lab. for Dependable Computing, Chalmers Univ. of Technol., Goteborg, Sweden
J. Ohlsson , Lab. for Dependable Computing, Chalmers Univ. of Technol., Goteborg, Sweden
J. Torin , Lab. for Dependable Computing, Chalmers Univ. of Technol., Goteborg, Sweden
ABSTRACT
A microprocessor error behavior function (EBF) is introduced, mapping faults into errors on the functional level. The errors are obtained using a functional model of the processor. By applying the EBF to a fault and instruction distribution, it is possible to obtain the corresponding error distribution. A case study is described, in which (i) the EBFs for simulated bit-flip and pin-level faults are designed and used to compare the bit-flip and pin-level fault models, and (ii) the obtained error distribution for the bit-flip faults is used in an error injection experiment on the functional level to emulate these faults. For the processor used in the case study, it was found that only 9-12% of the bit-flip faults could be emulated using pin-level faults, while a tentative evaluation of the possibility to emulate bit-flip faults with software-implemented fault injection showed that 98-99% could be emulated. Finally, the results of the emulated bit-flip errors corresponded well to the real results obtained using bit-flip faults, thus indicating that the injected errors are good approximations of the faults.<>
INDEX TERMS
computer testing, integrated circuit testing, microprocessor chips, fault location
CITATION

M. Rimen, J. Ohlsson and J. Torin, "On microprocessor error behavior modeling," Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing(FTCS), Austin, TX, USA, 1994, pp. 76-85.
doi:10.1109/FTCS.1994.315655
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