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Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing (1994)
Austin, TX, USA
June 15, 1994 to June 17, 1994
ISBN: 0-8186-5520-8
pp: 86-94
G.L. Ries , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
G.S. Choi , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
R.K. Iyer , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
ABSTRACT
This paper examines the accuracy of a discrete logic-level fault model often assumed in gate-level or discrete timing simulation. The analysis is done by comparing the faulty behavior predicted by the discrete model to that predicted by a circuit-level SPICE model whose accuracy is generally accepted. The comparison is made at both the subcircuit level, by measuring latch errors, and the system level, by measuring pin errors and data register errors, using the Motorola MC68000 as the target system. The results of the analysis show that the behavior predicted by the discrete model varies significantly from that of the circuit-level model when the injection site has multiple propagation paths to the circuit outputs (or latches) or is an internal node of one of the logic gates, even if the pulse width of the discrete transient is carefully chosen. However, the two models can be made to match for injection sites that are gate inputs or outputs and have only a single propagation path to circuit outputs. The differences in the latch errors predicted by the two models at the subcircuit level lead to over a 40% difference in the number of predicted pin errors and a 50% difference in the number of data errors predicted at the system level.<>
INDEX TERMS
circuit analysis computing, discrete event simulation, logic testing
CITATION

G. Ries, G. Choi and R. Iyer, "Device-level transient fault modeling," Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing(FTCS), Austin, TX, USA, 1994, pp. 86-94.
doi:10.1109/FTCS.1994.315654
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