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Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing (1994)
Austin, TX, USA
June 15, 1994 to June 17, 1994
ISBN: 0-8186-5520-8
pp: 96-105
D.A. Rennels , Comput. Sci. Dept., California State Univ., Los Angeles, CA, USA
Hyeongil Kim , Comput. Sci. Dept., California State Univ., Los Angeles, CA, USA
ABSTRACT
This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from Differential Cascode Voltage Switch Logic are compared with a checker that is composed of a tree of dual-rail (morphic) comparators to detect errors and signal completion. An efficient implementation is shown that compares favorably in speed and area with conventional completion signal generators. A simple pipeline is examined with error checkers at each computation stage and hand-shaking control circuits that are modified to improve error detection. Its error-detecting properties are discussed, and preliminary error simulation results are presented. Based on these studies we have concluded that self-timed logic offers considerable fault-tolerance potential due to its built-in redundancy that can be effectively exploited for error checking.<>
INDEX TERMS
VLSI, error detection, circuit reliability, logic testing, integrated circuit testing
CITATION

D. Rennels and Hyeongil Kim, "Concurrent error detection in self-timed VLSI," Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing(FTCS), Austin, TX, USA, 1994, pp. 96-105.
doi:10.1109/FTCS.1994.315653
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