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Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing (1994)
Austin, TX, USA
June 15, 1994 to June 17, 1994
ISBN: 0-8186-5520-8
pp: 106-115
F. Vargas , TIMA/INPG Lab., Grenoble, France
M. Nicolaidis , TIMA/INPG Lab., Grenoble, France
ABSTRACT
We present a new technique to improve the reliability of SRAMs used in space radiation environments. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of the memory cell being upset. The current checking is performed on the SRAM columns and it is combined with a single-parity bit per RAM word to perform error correction.<>
INDEX TERMS
SRAM chips, fault tolerant computing, error detection, error correction
CITATION

F. Vargas and M. Nicolaidis, "SEU-tolerant SRAM design based on current monitoring," Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing(FTCS), Austin, TX, USA, 1994, pp. 106-115.
doi:10.1109/FTCS.1994.315652
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