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Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing (1994)
Austin, TX, USA
June 15, 1994 to June 17, 1994
ISBN: 0-8186-5520-8
pp: 212-218
L. Tallini , Oregon State Univ., Corvallis, OR, USA
L. Merani , Oregon State Univ., Corvallis, OR, USA
B. Bose , Oregon State Univ., Corvallis, OR, USA
ABSTRACT
In a balanced code each codeword contains equal number of 1's and 0's. In this paper, methods for the construction of balanced codes, which use parallel encoding/decoding are described. The codes use fewer check bits and less hardware complexity than the existing codes.<>
INDEX TERMS
computational complexity, VLSI, codes
CITATION

L. Tallini, L. Merani and B. Bose, "Balanced codes for noise reduction in VLSI systems," Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing(FTCS), Austin, TX, USA, 1994, pp. 212-218.
doi:10.1109/FTCS.1994.315639
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