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Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing (1994)
Austin, TX, USA
June 15, 1994 to June 17, 1994
ISBN: 0-8186-5520-8
pp: 436-445
A. Mujumdar , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
R. Jain , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
K. Saluja , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
ABSTRACT
High-level synthesis tools automatically produce RTL designs from algorithmic specifications. These designs, however, are not necessarily easy to test. In this paper we present TBINET, an algorithm for module and register binding, which generates RTL designs having low testability overheads. It obtains a heuristic solution to the binding problem by mapping it onto a sequence of minimum cost network flow problems which can be solved very quickly. A cost function that considers the testability of the design is defined in the paper. The results of experiments on various benchmarks show that the designs produced by our binding algorithm are indeed easier to test as compared to circuits designed without testability considerations.<>
INDEX TERMS
design for testability, shift registers, logic CAD, formal specification
CITATION

A. Mujumdar, R. Jain and K. Saluja, "Behavioral synthesis of testable designs," Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing(FTCS), Austin, TX, USA, 1994, pp. 436-445.
doi:10.1109/FTCS.1994.315634
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