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Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing (1994)
Austin, TX, USA
June 15, 1994 to June 17, 1994
ISBN: 0-8186-5520-8
pp: 340-349
P. Liden , Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
P. Dahlgren , Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
R. Johansson , Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
J. Karlsson , Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
ABSTRACT
The question to what extent particle induced transients in combinational parts of a circuit propagate into memory elements is addressed in this paper An experimental method is presented in which the proportion of bit flips originating from heavy-ion hits in combinational logic is determined. It is proposed that a voltage pulse may only propagate through a limited number of transistor stages and still be latched. The proportion of all transients in combinational logic that were latched into registers was experimentally, estimated to be between 0.7/spl middot/10/sup -3/ and 2/spl middot/10/sup -3/ for a custom designed CMOS circuit. Very few multiple bit flips were observed during the experiments which indicates that the single bit flip model used in many high-level simulations is reasonable accurate.<>
INDEX TERMS
probability, flip-flops, combinatorial circuits, CMOS integrated circuits, circuit reliability, logic testing
CITATION

P. Liden, P. Dahlgren, R. Johansson and J. Karlsson, "On latching probability of particle induced transients in combinational networks," Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing(FTCS), Austin, TX, USA, 1994, pp. 340-349.
doi:10.1109/FTCS.1994.315626
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