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Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing (1994)
Austin, TX, USA
June 15, 1994 to June 17, 1994
ISBN: 0-8186-5520-8
pp: 456-465
P. Uppaluri , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
ABSTRACT
The problem of test generation for path delay faults in synchronous sequential circuits is addressed. In existing testing methods, a single fast clock cycle is used to activate path delay faults and a fault is said to be detected only if the fault free response is different from the faulty response at a single output and at a specified time unit in the test sequence. We refer to these methods as single fast clock cycle and single observation time testing methods. We show that testable faults may exist, which are untestable using a single fast clock cycle and a single observation time. Such faults are testable when multiple fast clock cycles and/or multiple observation times are used. A test generation procedure is given that uses multiple fast clock cycles and multiple observation times. Experimental results are presented on MCNC synthesis benchmarks to demonstrate the effectiveness of the proposed strategy in increasing the fault coverage and reducing the test length.<>
INDEX TERMS
logic testing, sequential circuits
CITATION

P. Uppaluri, I. Pomeranz and S. Reddy, "Test pattern generation for path delay faults in synchronous sequential circuits using multiple fast clocks and multiple observation times," Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing(FTCS), Austin, TX, USA, 1994, pp. 456-465.
doi:10.1109/FTCS.1994.315617
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