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Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium (1991)
Montreal, Quebec, Canada
June 25, 1991 to June 27, 1991
ISBN: 0-8186-2150-8
TABLE OF CONTENTS

Software defects and their impact on system availability-a study of field failures in operating systems (PDF)

M. Sullivan , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R. Chillarege , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 2-9

Error/failure analysis using event logs from fault tolerant systems (PDF)

I. Lee , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
R.K. Iyer , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
D. Tang , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 10-17

Fault tolerance testing in the Advanced Automation System (PDF)

T.R. Dilenno , IBM Federal Sector Div., Rockville, MD, USA
pp. 18-25

Fault-tolerance experiments of the 'Hiten' onboard space computer (PDF)

T. Takano , Inst. of Space & Astronaut Sci., Kanagawa, Japan
T. Yamada , Inst. of Space & Astronaut Sci., Kanagawa, Japan
K. Shutoh , Inst. of Space & Astronaut Sci., Kanagawa, Japan
pp. 26-33

TSUNAMI: a path oriented scheme for algebraic test generation (PDF)

T. Stanion , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
D. Bhattacharya , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
pp. 36-43

An architectural level test generator for a hierarchical design environment (PDF)

J. Lee , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 44-51

Test generation for synchronous sequential circuits using multiple observation times (PDF)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 52-59

Signature analysis with modified linear feedback shift registers (M-LFSRs) (PDF)

R. Raina , Dept. of Electr. Eng., Duke Univ., Durham, NC, USA
P.N. Marionos , Dept. of Electr. Eng., Duke Univ., Durham, NC, USA
pp. 88-95

Signature analysis and test scheduling for self-testable circuits (PDF)

A.P. Strole , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
H.-J. Wunderlich , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 96-103

Bounds on signature analysis aliasing for random testing (PDF)

N.R. Saxena , Dept. of Electr. Eng. & Comput. Sci., Stanford Uni., CA, USA
P. Franco , Dept. of Electr. Eng. & Comput. Sci., Stanford Uni., CA, USA
E.J. McCluskey , Dept. of Electr. Eng. & Comput. Sci., Stanford Uni., CA, USA
pp. 104-111

Construction and analysis of fault-secure multiprocessor schedules (PDF)

D. Gu , Dept. of Comput. Sci., State Univ. of New York, Albany, NY, USA
D.J. Rosenkrantz , Dept. of Comput. Sci., State Univ. of New York, Albany, NY, USA
S.S. Ravi , Dept. of Comput. Sci., State Univ. of New York, Albany, NY, USA
pp. 120-127

A fault-tolerant FFT processor (PDF)

M. Tsunoyama , Nagaoka Coll. of Technol., Niigata, Japan
pp. 128-135

Concurrent error detection and fault-tolerance in linear digital state variable systems (PDF)

A. Chatterjee , Gen. Electr. Res. & Dev. Center, Schenectady, NY, USA
M.A. d'Abreu , Gen. Electr. Res. & Dev. Center, Schenectady, NY, USA
pp. 136-143

Bridging, transition, and stuck-open faults in self-testing CMOS checkers (PDF)

S.D. Millman , Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA
E.J. McCluskey , Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA
pp. 154-161

Multiple fault analysis using a fault dropping technique (PDF)

A. Verreault , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
E.M. Aboulhamid , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
Y. Karkouri , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
pp. 162-169

VLSI implementation of a self-checking self-exercising memory system (PDF)

D.A. Rennels , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
H. Kim , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 170-177

The UCLA mirror processor: a building block for self-checking self-repairing computing nodes (PDF)

Y. Tamir , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
M. Liang , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
T. Lai , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
M. Tremblay , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 178-185

Load sharing in hypercube multicomputers in the presence of node failures (PDF)

Y.-C. Chang , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
K.G. Shin , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 188-195

Cost effectiveness analysis of different fault tolerance strategies for hypercube systems (PDF)

V. Grassi , Dipartimento di Ingegneria Elettronica, Roma II Univ., Italy
pp. 196-203

An evaluation of fault-tolerant hypercube architectures for onboard computing (PDF)

J.C. Peterson , Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
J.O. Tuazon , Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
E.T. Upchurch , Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
pp. 204-211

An adaptive distributed system-level diagnosis algorithm and its implementation (PDF)

R. Bianchini , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R. Buskens , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 222-229

Probabilistic diagnosis algorithms tailored to system topology (PDF)

S. Rangarajan , Maryland Univ., College Park, MD, USA
pp. 230-237

Certification trails for data structures (PDF)

G.F. Sullivan , Dept. of Comput. Sci., Johns Hopkins Univ., Baltimore, MD, USA
G.M. Masson , Dept. of Comput. Sci., Johns Hopkins Univ., Baltimore, MD, USA
pp. 240-247

Tolerating failures in the bag-of-tasks programming paradigm (PDF)

D.E. Bakken , Dept. of Comput. Sci., Arizona Univ., Tucson, AZ, USA
R.D. Schlichting , Dept. of Comput. Sci., Arizona Univ., Tucson, AZ, USA
pp. 248-255

Optimal broadcasting in faulty hypercubes (PDF)

B.S. Chlebus , Inst. Inf., Uniwersytet Warszawski, Poland
pp. 266-273

A multiple-fault tolerant sorting network (PDF)

J. Sun , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
J. Gecsei , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
pp. 274-281

Fault-tolerant gamma interconnection networks (PDF)

N.-F. Tzeng , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
P.-J. Chuang , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
pp. 282-289

Some practical issues in the design of fault-tolerant multiprocessors (PDF)

S. Dutt , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 292-299

A multiple copy approach for delivering messages under deadline constraints (PDF)

P. Ramanathan , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 300-307

State space generation for degradable multiprocessor systems (PDF)

B.E. Aupperle , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
J.F. Meyer , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 308-315

Exploiting instruction-level resource parallelism for transparent, integrated control-flow monitoring (PDF)

M.A. Schuette , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.P. Shen , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 318-325

Optimal signature placement for processor-error detection using signature monitoring (PDF)

K.D. Wilken , Dept. of Electr. Eng. & Comput. Sci., California Univ., Davis, CA, USA
pp. 326-333

A new approach to control flow checking without program modification (PDF)

T. Michel , Inst. Nat. Polytech. de Grenoble, France
R. Leveugle , Inst. Nat. Polytech. de Grenoble, France
G. Saucier , Inst. Nat. Polytech. de Grenoble, France
pp. 334-341

Fault-tolerant communications processing (PDF)

V. Cherkassky , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
H. Lari-Najafi , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 344-351

The RM recovery services (PDF)

D.V. Pitts , Dept. of Comput. Sci., Lowell Univ., MA, USA
pp. 360-367

Recovery concepts for data sharing systems (PDF)

E. Rahm , Dept. of Comput. Sci., Kaiserslautern Univ., Germany
pp. 368-375

Burst and unidirectional error detecting codes (PDF)

S. Al-Bassam , Fac. of Eng., Memorial Univ. of Newfoundland, St. John's, Nfld., Canada
pp. 378-384

Pattern sensitive fault testing of RAMs with built-in ECC (PDF)

M. Franklin , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
pp. 385-392

Gracefully degradable disk arrays (PDF)

A.L.N. Reddy , IBM Almaden Res. Center, San Jose, CA, USA
pp. 401-408

An experimental study on software structural testing: deterministic versus random input generation (PDF)

P. Thevenod-Fosse , LAAS-CNRS, Toulouse, France
H. Waeselynck , LAAS-CNRS, Toulouse, France
Y. Crouzet , LAAS-CNRS, Toulouse, France
pp. 410-417

Program fault tolerance based on memory access behavior (PDF)

N.S. Bowen , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 426-433

Distributed reconfiguration and recovery in the advanced architecture on-board processor (PDF)

M.J. Iacoponi , Harris Corp., Melbourne, FL, USA
S.F. McDonald , Harris Corp., Melbourne, FL, USA
pp. 436-443

On the reconfiguration of memory arrays containing clustered faults (PDF)

D.M. Blough , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
pp. 444-451

Reconfiguration algorithm for fault-tolerant arrays with minimum number of dangerous processors (PDF)

C. Chen , Dept. of Inf. & Comput. Sci., Osaka Univ., Japan
A. Feng , Dept. of Inf. & Comput. Sci., Osaka Univ., Japan
T. Kikuno , Dept. of Inf. & Comput. Sci., Osaka Univ., Japan
K. Torii , Dept. of Inf. & Comput. Sci., Osaka Univ., Japan
pp. 452-459

A distributed fault tolerant architecture for nuclear reactor and other critical process control applications (PDF)

M. Hecht , SoHaR In., Beverly Hills, CA, USA
J. Agron , SoHaR In., Beverly Hills, CA, USA
H. Hecht , SoHaR In., Beverly Hills, CA, USA
K.H. Kim , SoHaR In., Beverly Hills, CA, USA
pp. 462-498

Approaches to design of temporary blackout handling capabilities and an evaluation with a real-time tightly coupled network testbed (PDF)

K.H. Kim , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
W.J. Guan , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
A. Damm , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
pp. 470-477

The role of formal methods in the requirements analysis of safety-critical systems: a train set example (PDF)

A. Saeed , Comput. Lab., Newscastle upon Tyne Univ., UK
R. de Lemos , Comput. Lab., Newscastle upon Tyne Univ., UK
T. Anderson , Comput. Lab., Newscastle upon Tyne Univ., UK
pp. 478-485

System level diagnosis: Combining detection and location (PDF)

N.H. Vaidya , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
D.K. Pradhan , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 488-495

The t(n-1)-diagnosability and its applications to fault tolerance (PDF)

J. Xu , Comput. Lab., Newcastle upon Tyne Univ., UK
pp. 496-503

Design of multiprocessor systems for concurrent error detection and fault diagnosis (PDF)

B. Vinnakota , Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 504-511

Integrity S2: a fault-tolerant Unix platform (PDF)

D. Jewett , Tandem Comput. Inc., Cupertino, CA, USA
pp. 512-519
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