The Community for Technology Leaders
1989 The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers (1989)
Chicago, IL, USA
June 21, 1989 to June 23, 1989
ISBN: 0-8186-1959-7
TABLE OF CONTENTS

The fault tolerance approach of the Advanced Architecture Onboard Processor (PDF)

M.J. Iacoponi , Harris Corp., Melbourne, FL, USA
D.K. Vail , Harris Corp., Melbourne, FL, USA
pp. 6-12

Dependable onboard computer systems with a new method-stepwise negotiating voting (PDF)

N. Kanekawa , Hitachi Ltd., Ibaraki, Japan
H. Maejima , Hitachi Ltd., Ibaraki, Japan
pp. 13-19

Use of a functional programming model in fault tolerant parallel processing (PDF)

R. Harper , Charles Stark Draper Lab. Inc., Cambridge, MA, USA
G. Nagle , Charles Stark Draper Lab. Inc., Cambridge, MA, USA
M.A. Serrano , Charles Stark Draper Lab. Inc., Cambridge, MA, USA
pp. 20-26

An economical scan design for sequential logic test generation (PDF)

K.-T. Cheng , AT&T Bell Lab., Murray Hill, NJ, USA
V.D. Agrawal , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 28-35

Row/column pattern sensitive fault detection in RAMs via built-in self-test (PDF)

M. Franklin , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
pp. 36-43

Advanced automatic test pattern generation techniques for path delay faults (PDF)

M.H. Schulz , Dept. of Electr. Eng., Tech. Univ. of Munich, West Germany
K. Fuchs , Dept. of Electr. Eng., Tech. Univ. of Munich, West Germany
F. Fink , Dept. of Electr. Eng., Tech. Univ. of Munich, West Germany
pp. 44-51

On self-diagnosable multiprocessor systems: diagnosis by the comparison approach (PDF)

A. Sengupta , Dept. of Comput. Sci., Univ. of South Carolina, Columbia, SC, USA
pp. 54-61

Fault diagnosis for sparsely interconnected multiprocessor systems (PDF)

D.M. Blough , Dept. of Electr. Eng., California Univ., Irvine, CA, USA
pp. 62-69

Distributed syndrome decoding for regular interconnected structures (PDF)

A.K. Somani , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 70-77

Fault-tolerance in a high-speed 2D convolver/correlator: Starloc (PDF)

L.M. Napolitano , Sandia Nat. Lab., Livermore, CA, USA
D.D. Andaleon , Sandia Nat. Lab., Livermore, CA, USA
K.R. Berry , Sandia Nat. Lab., Livermore, CA, USA
P.R. Bryson , Sandia Nat. Lab., Livermore, CA, USA
S.R. Klapp , Sandia Nat. Lab., Livermore, CA, USA
J.E. Leeper , Sandia Nat. Lab., Livermore, CA, USA
pp. 80-87

Imperfectly connected 2D arrays for image processing (PDF)

J.A. Trotter , Dept. of Eng. Sci., Oxford Univ., UK
W.R. Moore , Dept. of Eng. Sci., Oxford Univ., UK
pp. 88-92

Comprehensive evaluation of a two-dimensional configurable array (PDF)

O. Menzilcioglu , Sch. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
H.T. Kung , Sch. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 93-100

Easily testable PLA-based finite state machines (PDF)

S. Devadas , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 102-109

The design of random-testable sequential circuits (PDF)

H.-J. Wunderlich , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., West Germany
pp. 110-117

BALLAST: a methodology for partial scan design (PDF)

R. Gupta , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
R. Gupta , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
M.A. Breuer , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 118-125

Design of fault-tolerant clocks with realistic failure assumptions (PDF)

N. Vasanthavada , Center for Digital Syst. Res., Research Triangle Inst., Research Triangle Park, NC, USA
pp. 128-133

A fast timing verification method based on the independence of units (PDF)

T. Yoneda , Tokyo Inst. of Technol., Japan
K. Nakade , Tokyo Inst. of Technol., Japan
Y. Tohma , Tokyo Inst. of Technol., Japan
pp. 134-141

Clock synchronization in MAFT (PDF)

P. Thambidurai , Allied-Signal Aerosp. Co., Columbia, MD, USA
pp. 142-149

Ultrahigh reliability estimates for systems exhibiting globally time-dependent failure processes (PDF)

R. Geist , Dept. of Comput. Sci., Clemson Univ., SC, USA
M. Smotherman , Dept. of Comput. Sci., Clemson Univ., SC, USA
M. Brown , Dept. of Comput. Sci., Clemson Univ., SC, USA
pp. 152-158

Evaluation of fault-tolerant systems with nonhomogeneous workloads (PDF)

B.E. Aupperle , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
J.F. Meyer , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
L. Wei , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 159-166

Modeling of fault-tolerant techniques in hierarchical systems (PDF)

Y.-B. Shieh , Dept. of Comput. Sci., Maryland Univ., Baltimore County, MD, USA
pp. 167-174

Performability of a token bus network under transient fault conditions (PDF)

J.F. Meyer , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 175-182

Distance agreement protocols (PDF)

K. Echtle , Karlsruhe Univ., West Germany
pp. 191-198

Some new EC/AUED codes (PDF)

J. Bruck , IBM Almaden Res. Center, San Jose, CA, USA
M. Blaum , IBM Almaden Res. Center, San Jose, CA, USA
pp. 208-215

Unidirectional 9-bit byte error detecting codes for computer memory systems (PDF)

L.A. Dunning , Dept. of Comput. Sci., Bowling Green State Univ., OH, USA
pp. 216-221

Byte unidirectional error correcting codes (PDF)

B. Bose , Dept. of Comput. Sci., Oregon State Univ., Corvallis, OR, USA
pp. 222-228

Design of efficient balanced codes (PDF)

S. Al-Bassam , Dept. of comput. Sci., Oregon State Univ., Corvallis, OR, USA
B. Bose , Dept. of comput. Sci., Oregon State Univ., Corvallis, OR, USA
pp. 229-236

Fault tolerant multiprocessor for digital switching systems (PDF)

T. Yamada , NTT Commun. Switching Lab., Tokyo, Japan
pp. 245-252

F-T in telecommunications networks: state, perspectives, trends (PDF)

M. Morganti , Italtel, Central Res. Labs., Milan, Italy
pp. 253-258

Reliable design of high-speed cache and control store memories (PDF)

R.W. Horst , Tandem Comput. Inc., Cupertino, CA, USA
pp. 259-266

A system for supporting multi-language versions for software fault tolerance (PDF)

J.M. Purtilo , Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA
P. Jalote , Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA
pp. 268-274

Fault identification in robust data structures (PDF)

A. Ravichandran , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
K. Kant , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
pp. 275-282

Formal verification of programs with exceptions (PDF)

J.-C. Bolot , Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA
P. Jalote , Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA
pp. 283-290

Computations over finite monoids and their test complexity (PDF)

B. Becker , Univ. of Saarland, Saarbruecken, West Germany
U. Sparmann , Univ. of Saarland, Saarbruecken, West Germany
pp. 299-306

A new approach of test confidence estimation (PDF)

M. Jacomino , Autom. Lab. of Grenoble ENSIEG/INPG, St.-Martin-d'Heres, France
R. David , Autom. Lab. of Grenoble ENSIEG/INPG, St.-Martin-d'Heres, France
pp. 307-314

Estimation of maximum currents for fault tolerant design of power distribution systems in integrated circuits (PDF)

S. Chowdhury , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 316-322

A proposal for a fault-tolerant binary hypercube architecture (PDF)

S.-C. Chau , Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
A.L. Liestman , Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 323-330

Message routing in HARTS with faulty components (PDF)

A. Olson , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
K.G. Shin , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 331-338

Evaluation of error detection schemes using fault injection by heavy-ion radiation (PDF)

U. Gunneflo , Dept. of Comput. Eng., Chalmers Univ. of Technol., Gothenburg, Sweden
J. Karlsson , Dept. of Comput. Eng., Chalmers Univ. of Technol., Gothenburg, Sweden
J. Torin , Dept. of Comput. Eng., Chalmers Univ. of Technol., Gothenburg, Sweden
pp. 340-347

Fault injection for dependability validation of fault-tolerant computing systems (PDF)

J. Arlat , Lab. of Autom. & Syst. Anal., CNRS, Toulouse, France
Y. Crouzet , Lab. of Autom. & Syst. Anal., CNRS, Toulouse, France
J.-C. Laprie , Lab. of Autom. & Syst. Anal., CNRS, Toulouse, France
pp. 348-355

Understanding large system failures-a fault injection experiment (PDF)

R. Chillarege , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
N.S. Bowen , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 356-363

Modelling correlated transient failures in fault-tolerant systems (PDF)

C.M. Krishna , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
A.D. Singh , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 374-381

Optimal control of latent fault accumulation (PDF)

M.J. Iacoponi , Harris Corp., Melbourne, FL, USA
pp. 382-388

A strongly fault-secure and strongly code-disjoint realization of combinational circuits (PDF)

T. Nanya , Tokyo Inst. of Technol., Japan
M. Uchida , Tokyo Inst. of Technol., Japan
pp. 390-397

A generalized theory of fail-safe systems (PDF)

M. Nicolaidis , IMAG/TIM3 Lab., Grenoble, France
S. Noraz , IMAG/TIM3 Lab., Grenoble, France
B. Courtois , IMAG/TIM3 Lab., Grenoble, France
pp. 398-406

Fault detection in CVS parity trees: application in SSC CVS parity and two-rail checkers (PDF)

N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 407-414

Control-flow checking using watchdog assists and extended-precision checksums (PDF)

N.R. Saxena , Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA
E.J. McCluskey , Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA
pp. 428-435

A study of time-redundant fault tolerance techniques for high-performance pipelined computers (PDF)

G.S. Sohi , Wisconsin Univ., Madison, WI, USA
M. Franklin , Wisconsin Univ., Madison, WI, USA
K.K. Saluja , Wisconsin Univ., Madison, WI, USA
pp. 436-443

A theoretical investigation of generalized voters for redundant systems (PDF)

P.R. Lorczak , Charles River Analytics Inc., Cambridge, MA, USA
A.K. Caglayan , Charles River Analytics Inc., Cambridge, MA, USA
pp. 444-451

CHAOS/sup art/: support for real-time atomic transactions (PDF)

A. Gheith , Sch. of Inf. & Comput. Sci., Georgia Inst. of Technol., Atlanta, GA, USA
K. Schwan , Sch. of Inf. & Comput. Sci., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 462-469

Language constructs for timed atomic commitment (PDF)

S. Davidson , Dept. of Comput. & Inf. Sci., Pennsylvania Univ., Philadelphia, PA, USA
I. Lee , Dept. of Comput. & Inf. Sci., Pennsylvania Univ., Philadelphia, PA, USA
V. Wolfe , Dept. of Comput. & Inf. Sci., Pennsylvania Univ., Philadelphia, PA, USA
pp. 470-477

Neural computing for built-in self-repair of embedded memory arrays (PDF)

P. Mazumder , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
J.-S. Yih , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 480-487

Bi-level reconfigurations of fault tolerant arrays in bi-modal computational environments (PDF)

R.G. Melhem , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
pp. 488-495

An automorphic approach to the design of fault-tolerant multiprocessors (PDF)

S. Dutt , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
J.P. Hayes , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 496-503

On the provision of backward error recovery in production programming languages (PDF)

S.T. Gregory , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
J.C. Knight , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 506-511

Hardware assisted recovery from transient errors in redundant processing systems (PDF)

S.J. Adams , Charles Stark Draper Lab., Cambridge, MA, USA
pp. 512-519

Recoverable distributed shared virtual memory: memory coherence and storage structures (PDF)

K.-L. Wu , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
W.K. Fuchs , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 520-527

An analytical model for computing hypercube availability (PDF)

C.R. Das , Dept. of Electr. Eng., Pennsylvania State Univ., University Park, PA, USA
J. Kim , Dept. of Electr. Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 530-537

Detailed modeling of fault-tolerant processor arrays (PDF)

N. Lopez-Benitez , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
J.A.B. Fortes , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 545-552

Characterization and design of sequentially t-diagnosable systems (PDF)

S. Huang , Comput. Res. Inst., Chongqing Univ., China
J. Xu , Comput. Res. Inst., Chongqing Univ., China
T. Chen , Comput. Res. Inst., Chongqing Univ., China
pp. 554-559

Probabilistic diagnosis of multiprocessor systems with arbitrary connectivity (PDF)

D. Fussell , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
S. Rangarajan , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 560-565

Reliability analysis and comparison of two fail-op/fail-op/fail-safe architectures (PDF)

A.K. Somani , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
T.R. Sarnaik , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 566-573
91 ms
(Ver 3.3 (11022016))