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1988 The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers (1988)
Tokyo, Japan
June 27, 1988 to June 30, 1988
ISBN: 0-8186-0867-6
TABLE OF CONTENTS

PODS revisited-a study of software failure behaviour (PDF)

P.G. Bishop , Central Electr. Res. Lab., Leatherhead, UK
F.D. Pullen , Central Electr. Res. Lab., Leatherhead, UK
pp. 2-8

In search of effective diversity: a six-language study of fault-tolerant flight control software (PDF)

A. Avizienis , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
M.R. Lyu , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
W. Schutz , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 15-22

Advanced automatic test pattern generation and redundancy identification techniques (PDF)

M.H. Schulz , Dept. of Electr. Eng., Tech. Univ. of Munich, West Germany
E. Auth , Dept. of Electr. Eng., Tech. Univ. of Munich, West Germany
pp. 30-35

Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits (PDF)

H.-J. Wunderlich , Inst. of Comput. Design & Fault-Tolerance, Karlsruhe Univ., West Germany
S. Hellebrand , Inst. of Comput. Design & Fault-Tolerance, Karlsruhe Univ., West Germany
pp. 36-41

Volatile logging in n-fault-tolerant distributed systems (PDF)

R.E. Strom , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
D.F. Bacon , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
S.A. Yemini , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 44-49

Approaches to implementation of a repairable distributed recovery block scheme (PDF)

K.H. Kim , Dept. of Electr. Eng., California Univ., Irvine, CA, USA
J.C. Yoon , Dept. of Electr. Eng., California Univ., Irvine, CA, USA
pp. 50-55

Fault tolerant concurrent C: a tool for writing fault tolerant distributed programs (PDF)

R.F. Cmelik , AT&T Bell Lab., Murray Hill, NJ, USA
N.H. Gehani , AT&T Bell Lab., Murray Hill, NJ, USA
W.D. Roome , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 56-61

Computational complexity of controllability/observability problems for combinational circuits (PDF)

H. Fujiwara , Dept. of Electron. & Commun., Meiji Univ., Kawasaki, Japan
pp. 64-69

An iterative technique for calculating aliasing probability of linear feedback signature registers (PDF)

A. Ivanov , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
V.K. Agarwal , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 70-75

RIDDLE: a foundation for test generation on a high level design description (PDF)

G.M. Silberman , Technion, Israel Inst. of Technol., Haifa, Israel
I. Spillinger , Technion, Israel Inst. of Technol., Haifa, Israel
pp. 76-81

Analysis of workload influence on dependability (PDF)

J.F. Meyer , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
L. Wei , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 84-89

Reliability analysis of non repairable systems using stochastic Petri nets (PDF)

K. Barkaoui , CNAM, Paris, France
G. Florin , CNAM, Paris, France
C. Fraize , CNAM, Paris, France
B. Lemaire , CNAM, Paris, France
S. Natkin , CNAM, Paris, France
pp. 90-95

An open layered architecture for dependability analysis and its application (PDF)

M. Mulazzani , Inst. for Tech. Inf., Tech. Univ. of Vienna, Austria
pp. 96-101

FIAT-fault injection based automated testing environment (PDF)

Z. Segall , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
D. Vrsalovic , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
D. Siewiorek , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 102-107

On simulating faults in parallel (PDF)

V.S. Iyengar , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
D.T. Tang , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 110-115

Accelerated fault simulation by propagating disjoint fault-sets (PDF)

S. Teshima , Toyota Central Res. & Dev. Lab. Inc., Aichi, Japan
N. Chujo , Toyota Central Res. & Dev. Lab. Inc., Aichi, Japan
N. Sano , Toyota Central Res. & Dev. Lab. Inc., Aichi, Japan
H. Nagase , Toyota Central Res. & Dev. Lab. Inc., Aichi, Japan
M. Takigawa , Toyota Central Res. & Dev. Lab. Inc., Aichi, Japan
pp. 116-121

A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits (PDF)

F. Maamari , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
J. Rajski , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 122-127

Dependability evaluation of software fault-tolerance (PDF)

J. Arlat , CNRS, Toulouse, France
K. Kanoun , CNRS, Toulouse, France
J.-C. Laprie , CNRS, Toulouse, France
pp. 142-177

Experimental evaluation of software reliability growth models (PDF)

K. Matsumoto , Dept. of Inf. & Comput. Sci., Osaka Univ., Japan
K. Inoue , Dept. of Inf. & Comput. Sci., Osaka Univ., Japan
T. Kikuno , Dept. of Inf. & Comput. Sci., Osaka Univ., Japan
K. Torii , Dept. of Inf. & Comput. Sci., Osaka Univ., Japan
pp. 148-153

A unified built-in-test scheme: UBIST (PDF)

M. Nicolaidis , TIM3/IMAG, Grenoble, France
pp. 157-163

An implementation and analysis of a concurrent built-in self-test technique (PDF)

R. Sharma , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
K.K. Saluja , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 164-169

An on-line error-detectable array divider with a redundant binary representation and a residue code (PDF)

N. Takagi , Dept. of Inf. Sci., Kyoto Univ., Japan
S. Yajima , Dept. of Inf. Sci., Kyoto Univ., Japan
pp. 174-179

General linear codes for fault-tolerant matrix operations on processor arrays (PDF)

V.S.S. Nair , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
J.A. Abraham , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 180-185

Watchdog parity channels for digital filter protection (PDF)

B. Zagar , Dept. of Electr. Eng. & Comput. Sci., California Univ., Davis, CA, USA
R. Redinbo , Dept. of Electr. Eng. & Comput. Sci., California Univ., Davis, CA, USA
pp. 186-191

Robust search methods for B-trees (PDF)

K. Fujimura , Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA
P. Jalote , Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA
pp. 194-199

Saturation: reduced idleness for improved fault-tolerance (PDF)

J.-C. Fabre , INRIA/LAAS, Toulouse, France
Y. Deswarte , INRIA/LAAS, Toulouse, France
pp. 200-205

Agreeing on who is present and who is absent in a synchronous distributed system (PDF)

F. Cristian , IBM Almaden Res. Center, San Jose, CA, USA
pp. 206-211

An easily testable parallel multiplier (PDF)

S.J. Hong , General Electric Co., Schenectady, NY, USA
pp. 214-219

On the design of robust testable CMOS combinational logic circuits (PDF)

S. Kundu , Dept. of Electr. & Comput. Eng., Iowa Univ., IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., IA, USA
pp. 220-225

The design of fast totally self-checking Berger code checkers based on Berger code partitioning (PDF)

J.-C. Lo , Southwestern Louisiana Univ., Lafayette, LA, USA
S. Thanawastien , Southwestern Louisiana Univ., Lafayette, LA, USA
pp. 226-231

The implementation and application of micro rollback in fault-tolerant VLSI systems (PDF)

Y. Tamir , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
M. Tremblay , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
D.A. Rennels , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 234-239

Hardware and software fault tolerance: a unified architectural approach (PDF)

J.H. Lala , Charles Stark Draper Lab. Inc., Cambridge, MA, USA
L.S. Alger , Charles Stark Draper Lab. Inc., Cambridge, MA, USA
pp. 240-245

Fault tolerant parallel processor architecture overview (PDF)

R.E. Harper , Charles Stark Draper Lab., Cambridge, MA, USA
J.H. Lala , Charles Stark Draper Lab., Cambridge, MA, USA
J.J. Deyst , Charles Stark Draper Lab., Cambridge, MA, USA
pp. 252-257

Almost certain diagnosis for intermittently faulty systems (PDF)

D.M. Blough , Dept. of Comput. Sci., Johns Hopkins Univ., Baltimore, MD, USA
G.F. Sullivan , Dept. of Comput. Sci., Johns Hopkins Univ., Baltimore, MD, USA
G.M. Masson , Dept. of Comput. Sci., Johns Hopkins Univ., Baltimore, MD, USA
pp. 260-265

On minimizing testing rounds for fault identification (PDF)

E. Schmeichel , Dept. of Math. & Comput. Sci., San Jose State Univ., CA, USA
pp. 266-271

A recursive procedure for optimally designing a hybrid fault diagnosable system (PDF)

T. Kohda , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
K.-I. Abiru , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
pp. 272-277

A probabilistic method for fault diagnosis of multiprocessor systems (PDF)

S. Rangarajan , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D. Fussell , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 278-283

Diagnostic reasoning in digital systems (PDF)

K.H. Thearling , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
R.K. Iyer , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 286-291

GEMINI-a logic system for fault diagnosis based on set functions (PDF)

J. Rajski , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 292-297

Reliabilities of two fault-tolerant interconnection networks (PDF)

J.T. Blake , Dept. of Comput. Sci., Duke Univ., Durham, NC, USA
K.S. Trivedi , Dept. of Comput. Sci., Duke Univ., Durham, NC, USA
pp. 300-305

Fault-tolerant BIBD networks (PDF)

B.E. Aupperle , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
J.F. Meyer , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 306-311

Disk dual copy methods and their performance (PDF)

Y. Dishon , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 314-319

Reliable design of large crosspoint switching networks (PDF)

A. Varma , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
J. Ghosh , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
C.J. Georgiou , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 320-325

Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures (PDF)

S. Dutt , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
J.P. Hayes , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 328-333

A fault-tolerant parallel processor modeled by a linear cellular automaton (PDF)

M. Tsunoyama , Fac. of Eng., Technol. Univ. of Nagaoka, Japan
S. Naito , Fac. of Eng., Technol. Univ. of Nagaoka, Japan
pp. 334-339

Approaches for the repair of VLSI/WSI RRAMs by row/column deletion (Abstract)

F. Lombardi , Dept. of Comput. Sci., Texas A&M Univ., College station, TX, USA
pp. 342-347

Minimum fault coverage in reconfigurable arrays (PDF)

N. Hasan , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
C.L. Liu , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 348-353

Masking asymmetric line faults using semi-distance codes (PDF)

K. Matsuzawa , Commun. & Inf. Process. Lab., NTT, Tokyo, Japan
E. Fujiwara , Commun. & Inf. Process. Lab., NTT, Tokyo, Japan
pp. 354-359

An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor (Abstract)

P. Banerjee , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
J.T. Rahmeh , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
C.B. Stunkel , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
V.S.S. Nair , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
K. Roy , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
J.A. Abraham , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 362-367

An efficient multi-dimensional grids reconfiguration algorithm on hypercube (PDF)

S.K. Chen , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
C.T. Liang , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
W.T. Tsai , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 368-373

Multiple stuck-at fault testability of self-testing checkers (PDF)

T. Nanya , Dept. of Comput. Sci., Tokyo Inst. of Technol., Japan
pp. 381-386
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