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Proceedings IEEE Symposium on FPGAs for Custom Computing Machines (1996)
Napa Valley, CA, USA
April 17, 1996 to April 19, 1996
ISBN: 0-8186-7548-9
TABLE OF CONTENTS

VLSI architectures for field programmable gate arrays: a case study (PDF)

Woods , Inst. of Adv. Microelectron., Queen's Univ., Belfast, UK
pp. 2-9

Assessing document relevance with run-time reconfigurable machines (PDF)

Gunther , Sch. of Comput. & Inf. Sci., Univ. of South Australia, The Levels, SA, Australia
pp. 10-17

A software development system for FPGA-based data acquisition systems (PDF)

Wenban , Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
pp. 28-37

Bit-serial pipeline synthesis for multi-FPGA systems with C++ design capture (PDF)

Isshiki , Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
pp. 38-47

Revisiting Smalltalk-80 blocks: a logic generator for FPGAs (PDF)

Pottier , Univ. de Bretagne Occidentale, Brest, France
pp. 48-57

RACER: a reconfigurable constraint-length 14 Viterbi decoder (PDF)

Yeh , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 60-69

Using rapid prototyping to teach the design of complete computing solutions (PDF)

Athanas , Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
pp. 90-97

Implementation of IEEE single precision floating point addition and multiplication on FPGAs (PDF)

Louca , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
pp. 107-116

Mixing fixed and reconfigurable logic for array processing (PDF)

Bakkes , Dept. of Electr. & Electron. Eng., Stellenbosch Univ., South Africa
pp. 118-125

OneChip: an FPGA processor with reconfigurable logic (PDF)

Wittig , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 126-135

Modelling and optimising run-time reconfigurable systems (PDF)

Luk , Dept. of Comput., Imperial Coll. of Sci., Technol. & Med., London, UK
pp. 167-176

Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures (PDF)

Peterson , Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
pp. 178-187

Expressing dynamic reconfiguration by partial evaluation (PDF)

Singh , Dept. of Comput. Sci., Glasgow Univ., UK
pp. 188-194

Supporting FPGA microprocessors through retargetable software tools (PDF)

Clark , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
pp. 195-203

On the viability of FPGA-based integrated coprocessors (PDF)

Albaharna , Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
pp. 206-215

A quantitative analysis of processor-programmable logic interface (PDF)

Rajamani , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 226-234

Author index (PDF)

pp. 235
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