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Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines (1994)
Napa Valley, CA, USA
April 10, 1994 to April 13, 1994
ISBN: 0-8186-5490-2
TABLE OF CONTENTS

A case study on hardware/software partitioning (PDF)

A. Jantsch , ESD Lab., R. Inst. of Technol., Stockholm, Sweden
P. Ellervee , ESD Lab., R. Inst. of Technol., Stockholm, Sweden
J. Oberg , ESD Lab., R. Inst. of Technol., Stockholm, Sweden
A. Hemani , ESD Lab., R. Inst. of Technol., Stockholm, Sweden
pp. 111-118

From high level programming model to FPGA machines (PDF)

J.P. Banatre , Campus de Beaulieu, IRISA, Rennes, France
D. Lavenier , Campus de Beaulieu, IRISA, Rennes, France
M. Vieillot , Campus de Beaulieu, IRISA, Rennes, France
pp. 119-124

Behavioral synthesis for FPGA-based computing (PDF)

H. Schmit , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L. Amstein , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D. Thomas , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
E. Lagnese , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 125-132

A field programmable multi-chip module (FPMCM) (PDF)

J. Darnauer , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
P. Garay , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
T. Isshiki , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
J. Ramirez , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
W. Wei-Ming Dai , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 1-10

Pin assignment for multi-FPGA systems (PDF)

S. Hauck , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
G. Borriello , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 11-13

Emulation of the Sparcle microprocessor with the MIT Virtual Wires emulation system (PDF)

M. Dahl , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
J. Babb , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
R. Tessier , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
S. Hanono , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
D. Hoki , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
A. Agarwal , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
pp. 14-22

The Nano Processor: a low resource reconfigurable processor (PDF)

M.J. Wirthlin , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
B.L. Hutchings , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
pp. 23-30

DPGA-coupled microprocessors: commodity ICs for the early 21st Century (PDF)

A. DeHon , Artificial Intelligence Lab., MIT, Cambridge, MA, USA
pp. 31-39

Field programmable gate array based reconfigurable preprocessor (PDF)

B. Box , Lockheed Sanders, Nashua, NH, USA
pp. 40-48

Virtual hardware for graphics applications using FPGAs (PDF)

S. Singh , Dept. of Comput. Sci., Glasgow Univ., UK
pp. 49-58

PAM programming environments: practice and experience (PDF)

P. Bertin , Paris Res. Lab., Digital Equipment Corp., Rueil-Malmaison, France
H. Touati , Paris Res. Lab., Digital Equipment Corp., Rueil-Malmaison, France
pp. 133-138

A reconfigurable Monte-Carlo clustering processor (MCCP) (PDF)

C.P. Cowen , Dept. of Electron. Syst. Eng., Essex Univ., Colchester, UK
pp. 59-65

CAFCA (Compact Accelerator For Cellular Automata): the metamorphosable machine (PDF)

P. Marchal , Centre Suisse d'Electronique et de Microtechnique SA, Neuchatel, Switzerland
pp. 66-71

A reconfigurable data-driven ALU for Xputers (PDF)

R.W. Hartenstein , Kaiserslautern Univ., Germany
R. Kress , Kaiserslautern Univ., Germany
H. Reinig , Kaiserslautern Univ., Germany
pp. 139-146

Global control synthesis for an MIMD/FPGA machine (PDF)

P. Dhaussy , Lab. d'Inf. de Brest, Univ. de Bretagne Occidentale, Brest, France
J.-M. Filloque , Lab. d'Inf. de Brest, Univ. de Bretagne Occidentale, Brest, France
B. Pottier , Lab. d'Inf. de Brest, Univ. de Bretagne Occidentale, Brest, France
S. Rubini , Lab. d'Inf. de Brest, Univ. de Bretagne Occidentale, Brest, France
pp. 72-81

Hardware-software codesign of multidimensional programs (PDF)

W. Luk , Comput. Lab., Oxford Univ., UK
T. Wu , Comput. Lab., Oxford Univ., UK
I. Page , Comput. Lab., Oxford Univ., UK
pp. 82-90

A reconfigurable compute engine for real-time vision automata prototyping (PDF)

G.M. Quenot , Lab. Syst. de Perception, Etablissement Tech. Central de l'Armement, Arcueil, France
I.C. Kraljic , Lab. Syst. de Perception, Etablissement Tech. Central de l'Armement, Arcueil, France
J. Serot , Lab. Syst. de Perception, Etablissement Tech. Central de l'Armement, Arcueil, France
B. Zavidovique , Lab. Syst. de Perception, Etablissement Tech. Central de l'Armement, Arcueil, France
pp. 91-100

An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs (PDF)

L. Agarwal , Div. of Eng., Brown Univ., Providence, RI, USA
M. Wazlowski , Div. of Eng., Brown Univ., Providence, RI, USA
S. Ghosh , Div. of Eng., Brown Univ., Providence, RI, USA
pp. 101-110

Compiling to the gate level for a reconfigurable co-processor (PDF)

D. Wo , Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia
K. Forward , Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia
pp. 147-154

Finding lines and building pyramids with SPLASH 2 (PDF)

A.L. Abbott , Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
P.M. Athanas , Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
L. Chen , Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
R.L. Elliott , Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
pp. 155-163

Comparing the performance of FPGA-based custom computers with general-purpose computers for DSP applications (PDF)

N.W. Bergmann , Joint Res Centre in Inf. Technol., Flinders Univ., Adelaide, SA, Australia
J.C. Mudge , Joint Res Centre in Inf. Technol., Flinders Univ., Adelaide, SA, Australia
pp. 164-171

An FPGA-based custom coprocessor for automatic image segmentation applications (PDF)

G.J. Gent , Dept. of Electr. Eng., Southern Illinois Univ., Edwardsville, IL, USA
S.R. Smith , Dept. of Electr. Eng., Southern Illinois Univ., Edwardsville, IL, USA
R.L. Haviland , Dept. of Electr. Eng., Southern Illinois Univ., Edwardsville, IL, USA
pp. 172-179

Density enhancement of a neural network using FPGAs and run-time reconfiguration (PDF)

J.G. Eldredge , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
B.L. Hutchings , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
pp. 180-188

FPGA-based stochastic neural networks-implementation (PDF)

S.L. Bade , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
B.L. Hutchings , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
pp. 189-198
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