The Community for Technology Leaders
Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines (1993)
Napa, CA, USA
April 5, 1993 to April 7, 1993
ISBN: 0-8186-3890-7
TABLE OF CONTENTS

A stochastic neural architecture that exploits dynamically reconfigurable FPGAs (PDF)

M. van Daalen , Dept. of Comput. Sci., R. Holloway Univ. of London, Egham, UK
P. Jeavons , Dept. of Comput. Sci., R. Holloway Univ. of London, Egham, UK
J. Shawe-Taylor , Dept. of Comput. Sci., R. Holloway Univ. of London, Egham, UK
pp. 202-211

Hardware acceleration of divide-and-conquer paradigms: a case study (PDF)

W. Luk , Oxford Univ. Comput. Lab., UK
V. Lok , Oxford Univ. Comput. Lab., UK
I. Page , Oxford Univ. Comput. Lab., UK
pp. 192-201

Searching genetic databases on Splash 2 (PDF)

D.T. Hoang , Dept. of Comput. Sci., Brown Univ., Providence, RI, USA
pp. 185-191

A digit-recurrence square root implementation for field programmable gate arrays (PDF)

M.E. Louie , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
M.D. Ercegovac , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 178-183

Text searching on Splash 2 (PDF)

D.V. Pryor , Supercomputing Res. Center, Bowie, MD, USA
M.R. Thistle , Supercomputing Res. Center, Bowie, MD, USA
N. Shirazi , Supercomputing Res. Center, Bowie, MD, USA
pp. 172-177

Data-folding in SRAM configurable FPGAs (PDF)

P.W. Foulk , Heriot-Watt Univ., Edinburgh, UK
pp. 163-171

Architectural tradeoffs in field-programmable-device-based computing systems (PDF)

P.K. Chan , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
M.D.F. Schlag , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 152-161

Virtual wires: overcoming pin limitations in FPGA-based logic emulators (PDF)

J. Babb , MIT Lab. for Comput. Sci., Cambridge, MA, USA
R. Tessier , MIT Lab. for Comput. Sci., Cambridge, MA, USA
A. Agarwal , MIT Lab. for Comput. Sci., Cambridge, MA, USA
pp. 142-151

The CM-2X: a hybrid CM-2/Xilinx prototype (PDF)

S.A. Cuccaro , Inst. for Defense Analyses, Supercomputing Res. Center, Bowie, MD, USA
C.F. Reese , Inst. for Defense Analyses, Supercomputing Res. Center, Bowie, MD, USA
pp. 121-130

A reconfigurable computer for embedded control applications (PDF)

H.-J. Herpel , Inst. of Microelectronic Syst., Darmstadt Univ. of Technol., Germany
N. Wehn , Inst. of Microelectronic Syst., Darmstadt Univ. of Technol., Germany
M. Gasteier , Inst. of Microelectronic Syst., Darmstadt Univ. of Technol., Germany
M. Glesner , Inst. of Microelectronic Syst., Darmstadt Univ. of Technol., Germany
pp. 111-120

Reconfigurable multi-bit processor for DSP applications in statistical physics (PDF)

S. Monaghan , Dept. of Electron. Syst. Eng., Essex Univ., Colchester, UK
C.P. Cowen , Dept. of Electron. Syst. Eng., Essex Univ., Colchester, UK
pp. 103-110

FPGA computing in a data parallel C (PDF)

M. Gokhale , Supercomputing Res. Center, Bowie, MD, USA
R. Minnich , Supercomputing Res. Center, Bowie, MD, USA
pp. 94-101

The Splash 2 software environment (PDF)

J.M. Arnold , IDA Supercomputing Res. Center, Bowie, MD, USA
pp. 88-93

A data-parallel programming model for reconfigurable architectures (PDF)

S.A. Guccione , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M.J. Gonzalez , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 79-87

The AnyBoard: programming and enhancements (PDF)

D.E. Van den Bout , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 68-77

A field programmable accelerator for compiled-code applications (PDF)

D.M. Lewis , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
M.H. van Ierssel , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
D.H. Wong , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
pp. 60-67

A self-reconfigurable processor (PDF)

P.C. French , Dept. of Electron., York Univ., Heslington, UK
R.W. Taylor , Dept. of Electron., York Univ., Heslington, UK
pp. 50-59

Virtual computing and the Virtual Computer (PDF)

S. Casselman , Virtual Comput. Corp., Reseda, CA, USA
pp. 43-48

WASMII: a data driven computer on a virtual hardware (PDF)

X.-P. Ling , Dept. of Electr. Eng., Keio Univ., Yokohama, Japan
H. Amano , Dept. of Electr. Eng., Keio Univ., Yokohama, Japan
pp. 33-42

Realising massively concurrent systems on the SPACE machine (PDF)

G. Milne , Dept. of Comput. Sci., Strathclyde Univ., Glasgow, UK
P. Cockshott , Dept. of Comput. Sci., Strathclyde Univ., Glasgow, UK
G. McCaskill , Dept. of Comput. Sci., Strathclyde Univ., Glasgow, UK
P. Barrie , Dept. of Comput. Sci., Strathclyde Univ., Glasgow, UK
pp. 26-32

Spyder: a reconfigurable VLIW processor using FPGAs (PDF)

C. Iseli , Logic Syst. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
E. Sanchez , Logic Syst. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
pp. 17-24

PRISM-II compiler and architecture (PDF)

M. Wazlowski , Lab. for Eng., Brown Univ., Providence, RI, USA
L. Agarwal , Lab. for Eng., Brown Univ., Providence, RI, USA
T. Lee , Lab. for Eng., Brown Univ., Providence, RI, USA
A. Smith , Lab. for Eng., Brown Univ., Providence, RI, USA
E. Lam , Lab. for Eng., Brown Univ., Providence, RI, USA
P. Athanas , Lab. for Eng., Brown Univ., Providence, RI, USA
H. Silverman , Lab. for Eng., Brown Univ., Providence, RI, USA
S. Ghosh , Lab. for Eng., Brown Univ., Providence, RI, USA
pp. 9-16

Fine grain parallelism on a MIMD machine using FPGAs (PDF)

F. Raimbault , IRISA, Rennes, France
D. Lavenier , IRISA, Rennes, France
pp. 2-8
86 ms
(Ver 3.3 (11022016))