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Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) (1993)
Beijing, China
Nov. 16, 1993 to Nov. 18, 1993
ISBN: 0-8186-3930-X
TABLE OF CONTENTS

Universal test set generation for CMOS circuits (PDF)

B. Chen , Dept. of Electron. Eng. & Inst. of Electron., National Chiao Tung Univ., Hsin-Chu, Taiwan
pp. 20-25

An algorithm for test generation of combinational circuits - research and implementation for critical path tracing (PDF)

S. Yin , Inst. of Comput. Technol., Beijing, China
D.-Z. Wei , Inst. of Comput. Technol., Beijing, China
pp. 26-30

Reliable fail-safe systems (PDF)

M. Lubaszewski , INPG/TIMA, Grenoble, France
B. Courtois , INPG/TIMA, Grenoble, France
pp. 32-37

Study of fault propagation using fault injection in the UNIX system (PDF)

W.-L. Kao , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
D. Tang , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
R.K. Iyer , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 38-43

Neural network realization of Markov model of TMR systems with compensating failures (PDF)

Y. Zhou , Inst. of Comput. Technol., Academia Sinica, Beijing, China
Y. Min , Inst. of Comput. Technol., Academia Sinica, Beijing, China
pp. 44-48

Software upset analysis: A case study of the HS1602 microprocessor (PDF)

G.S. Choi , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
R.K. Iyer , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 49-54

A distributed message routing algorithm for fault-tolerant hypercube systems (PDF)

Y.-L. Min , Inst. of Comput. Technol., Academia Sinica, Beijing, China
Y. Min , Inst. of Comput. Technol., Academia Sinica, Beijing, China
pp. 55-58

A two-phase fault simulation scheme for sequential circuits (PDF)

W.C. Wu , Dept. of Electron. Eng. & Inst. of Electron., National Chiao Tung Univ., Hsin-Chu, Taiwan
pp. 60-65

On the eliminating of parameters /spl alpha/ and /spl beta/ in STAFAN (PDF)

J. Ding , Beijing Univ. of Posts & Telecommun., Beijing, China
pp. 72-74

Parallel computation of LFSR signatures (PDF)

B. Narendran , Dept. of Comput. Sci. Wisconsin Univ., Madison, WI, USA
M. Franklin , Dept. of Comput. Sci. Wisconsin Univ., Madison, WI, USA
pp. 75-80

An approach to the analysis of the current testability of IC analog sections (PDF)

D. Mateo , Electron. Eng. Dept., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 82-87

Subjective fault evaluation method of electronic circuits (PDF)

M. Hashizume , Fac. of Eng., Tokushima Univ., Japan
Y. Iwata , Fac. of Eng., Tokushima Univ., Japan
T. Tamesada , Fac. of Eng., Tokushima Univ., Japan
pp. 94-99

Test generation for E-beam testing of VLSI circuits (PDF)

O.C.S. Choy , Chinese Univ. of Hong Kong, Hong Kong
L.K. Chan , Chinese Univ. of Hong Kong, Hong Kong
R. Chan , Chinese Univ. of Hong Kong, Hong Kong
C.F. Chan , Chinese Univ. of Hong Kong, Hong Kong
pp. 101-106

PLANE: A new ATPG system for PLAs (PDF)

J.-D. Huang , Dept. of Electron. Eng., National Chiao Tung Univ., Hsinchu, Taiwan
pp. 107-112

A 15-valued fast test generation for combinational circuits (PDF)

S.J. Hong , Dept. of Comput. Sci., Pohang Inst. of Sci. & Technol., South Korea
pp. 113-118

Optimization of deterministic test sets using an estimation of product quality (PDF)

G. Spiegel , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 119-124

Testing of parallel programs based on primitive dependence graph (PDF)

H.-P. Wu , Dept. of Comput. Sci., Changsha Inst. of Technol., Changsha, Hunan, China
pp. 126-131

An approach to large program testing with tool WHEN (PDF)

H. Zhu , Dept. of Comput. Sci., Changsha Inst. of Technol., China
F. Chen , Dept. of Comput. Sci., Changsha Inst. of Technol., China
pp. 132-137

Test sequence algorithms and formal languages (PDF)

S.P. van de Burgt , PTT Res., Leidschendam, Netherlands
pp. 138-146

A new method for system diagnosis (PDF)

S. Xu , Shanghai Univ. of Sci. & Technol., China
pp. 147-152

A global BIST methodology (PDF)

T. Gheewala , CrossCheck Technology, Inc., San Jose, CA, USA
H. Sucar , CrossCheck Technology, Inc., San Jose, CA, USA
P. Varma , CrossCheck Technology, Inc., San Jose, CA, USA
pp. 154-159

LFSROM: A hardware test pattern generator for deterministic ISCAS85 test sets (PDF)

C. Dufaza , Lab. d'Inf., de Robotique et de Micro-electronique de Montpellier, France
C. Chevalier , Lab. d'Inf., de Robotique et de Micro-electronique de Montpellier, France
L.F.C. Lew Yan Voon , Lab. d'Inf., de Robotique et de Micro-electronique de Montpellier, France
pp. 160-165

Additive cellular automata as an on-chip test pattern generator (PDF)

S. Nandi , Dept. of Comput. Sci. & Engg., Indian Inst. of Technol., Kharagpur, India
pp. 166-171

T-BIST: A built-in self-test for analog circuits based on parameter translation (PDF)

M. Slamani , Dept. of Electr. Eng. Ecole Polytech. de Montreal, Que., Canada
pp. 172-177

The complexity of determining the sequential diagnosability number in the Malek's comparison model (PDF)

Zhou Liuding , Dept. of Comput., Chongqing Univ., China
Yang Xiaofan , Dept. of Comput., Chongqing Univ., China
Chen Tinghuai , Dept. of Comput., Chongqing Univ., China
Tang Chenli , Dept. of Comput., Chongqing Univ., China
pp. 191-196

Optimal interconnect diagnosis (PDF)

W. Shi , Dept. of Comput. Sci., North Texas Univ., Denton, TX, USA
pp. 197-200

A C-testable DCVS GF(2/sup m/) multiplier (PDF)

T.-Y. Chang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
J.-H. Chen , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 204-209

The driver/receiver conflict problem in interconnect testing with boundary-scan (PDF)

L. Jin , Vertex Semiconductor, San Jose, CA, USA
pp. 210-214

Design and implementation of a JTAG boundary-scan interface controller (PDF)

Shen Xu Baang , ShaanXi Microelectron. Res. Inst., China
Liang Song Hai , ShaanXi Microelectron. Res. Inst., China
pp. 215-218

A systematic method to classify scan cells (PDF)

K.-J. Lee , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
M.-H. Lu , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
J.-F. Wang , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 219-224

GID-testable two-dimensional sequential arrays for self-testing (PDF)

W.K. Huang , Dept. of EE, Fudan Univ., Shanghai, China
pp. 225-229

A current testing for CMOS static RAMs to reduce testing costs (PDF)

H. Yokoyama , Dept. of Inf. Eng., Akita Univ., Japan
H. Tamamoto , Dept. of Inf. Eng., Akita Univ., Japan
Y. Narita , Dept. of Inf. Eng., Akita Univ., Japan
pp. 231-236

Fault modelisation of external shorts in CMOS circuits (PDF)

M. Renovell , Lab. d'Inf., Univ. de Montpellier II, France
P. Huc , Lab. d'Inf., Univ. de Montpellier II, France
Y. Bertrand , Lab. d'Inf., Univ. de Montpellier II, France
pp. 237-242

Limitations of built-in current sensors (BICS) for I/sub DDQ/ testing (PDF)

S.M. Menon , Colorado State Univ., Ft. Collins, CO, USA
Y.K. Malaiya , Colorado State Univ., Ft. Collins, CO, USA
A.P. Jayasumana , Colorado State Univ., Ft. Collins, CO, USA
C.Q. Tong , Colorado State Univ., Ft. Collins, CO, USA
pp. 243-248

Effectiveness of stuck-at test sets to detect bridging faults in Iddq environment (PDF)

S. Hwang , Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
R. Rajsuman , Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
pp. 249-254

Automatic fault location using E-beam and LSI testers (PDF)

N. Itazaki , Dept. of Appl. Phys., Osaka Univ., Suita, Japan
T. Sumioka , Dept. of Appl. Phys., Osaka Univ., Suita, Japan
S. Kajihara , Dept. of Appl. Phys., Osaka Univ., Suita, Japan
K. Kinoshita , Dept. of Appl. Phys., Osaka Univ., Suita, Japan
pp. 255-260

Testing scheduling and control in a parallel processing environment (PDF)

Xiang Dong , Inst. of Comput. Technol., Academia Sinica, Beijing, China
pp. 262-267

On the testability of cascaded Reed Muller circuits (PDF)

G. Lee , Dept. of Comput. Sci., Chonnam Nat. Univ., Kwangju, South Korea
M. Hwang , Dept. of Comput. Sci., Chonnam Nat. Univ., Kwangju, South Korea
pp. 268-273

Detection of multiple faults using SSFTS in CMOS logic circuits (PDF)

C.Q. Tong , Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
D. Lu , Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
pp. 274-279

Design of efficient totally self-checking checkers for m-out-of-n code (PDF)

W.-F. Chang , Dept. of Comput. Sci., National Tsin Hua Univ., Hsinchu, Taiwan
pp. 281-286

General design principles of self-testing code-disjoint PLAs (PDF)

S.J. Piestrak , Inst. of Eng. Cybernetics, Tech. Univ. of Wroclaw, Poland
pp. 287-292

State encoding and functional decomposition for self-checking sequential circuit design (PDF)

S. Pagey , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
pp. 293-297

Design of monitored self-checking sequential circuits for enhanced fault models (PDF)

R.A. Parekhji , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
G. Venkatesh , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
S.D. Sherlekar , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
pp. 298-303

On properties and implementations of inverting ALSC for use in built-in self-testing (PDF)

K. Furuya , Fac. of Sci. & Eng., Chuo Univ., Tokyo, Japan
P.Y. Koh , Fac. of Sci. & Eng., Chuo Univ., Tokyo, Japan
pp. 305-310

Achieving minimal hardware multiple signature analysis for BIST (PDF)

Y. Wu , Bell-Northern Research, Ltd., Ottawa, Ont., Canada
pp. 311-316

Error localization in test outputs: A generalized analysis of signature compression (PDF)

S. Demidenko , Inst. of Eng. Cybernetics, Byelorussian Acad. of Sci., Minsk, Byelorussia
pp. 317-322

Application of homing sequences to synchronous sequential circuit testing (PDF)

I. Pomeranz , Electr. & Comput. Eng. Dept., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Electr. & Comput. Eng. Dept., Iowa Univ., Iowa City, IA, USA
pp. 324-329

Computer aided testing system for LC cell's optical properties (PDF)

Jiang Min , Changchun Inst. of Phys., Academia Sinica, China
Huang Ximin , Changchun Inst. of Phys., Academia Sinica, China
Wang Zhongkai , Changchun Inst. of Phys., Academia Sinica, China
Lin Zhihua , Changchun Inst. of Phys., Academia Sinica, China
pp. 330-332

Bayesian inference for fault diagnosis in real-time distributed systems (PDF)

Y.L.C. Chang , Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
L.C. Lander , Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
pp. 333-338
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