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Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (2001)
Yokohama, Japan
Feb. 2, 2001 to Feb. 2, 2001
ISBN: 0-7803-6633-6
TABLE OF CONTENTS

Multi-hit time-to-digital converter VLSI for high-energy physics experiments (PDF)

Y. Arai , Inst. of Particle & Nucl. Studies, Nat. High Energy Accelerator Res. Organ., Tsukuba, Japan
pp. 5-6

High-speed FIR digital filter with CSD coefficients implemented on FPGA (PDF)

M. Yamada , Graduate Sch. of Sci. & Eng., Tokyo Inst. of Technol., Japan
pp. 7-8

A prototype chip of multicontext FPGA with DRAM for virtual hardware (PDF)

D. Kawakami , Dept. of Comput. Sci., Keio Univ., Yokohama, Japan
pp. 17-18

A smart position sensor for 3-D measurement (PDF)

T. Nezuka , Dept. of Electron. Eng., Tokyo Univ., Japan
pp. 21-22

Parameterized MAC unit implementation (PDF)

Ming-Chih Chen , Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
pp. 23-24

An 8-b nRERL microprocessor for ultra-low-energy applications (PDF)

Seokkee Kim , Syst. Design Group, Seoul Nat. Univ., South Korea
pp. 27-28

Reusable embedded in-circuit emulator (PDF)

Ing-Jer Huang , Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
pp. 33-34

Flexible processor based on full-adder/D-flip-flop merged module (PDF)

S. Sakaidani , Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan
pp. 35-36

Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communication (PDF)

T. Okuma , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
pp. 37-38

Compiling SpecC for simulation (PDF)

Jianwen Zhu , Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 57-62

Application of linearly transformed BDDs in sequential verification (PDF)

W. Gunther , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
pp. 91-96

An efficient design-for-verification technique for HDLs (PDF)

C.-N.J. Liu , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 103-108

Reducing bus delay in submicron technology using coding (PDF)

P.P. Sotiriadis , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 109-114

Optimal spacing and capacitance padding for general clock structures (PDF)

Yu-Min Lee , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 115-119

Construction of minimal delay Steiner tree using two-pole delay model (PDF)

Li Yi Lin , Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 126-131

Hierarchical dummy fill for process uniformity (PDF)

Yu Chen , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 139-144

Modeling and forecasting of manufacturing variations (PDF)

S.R. Nassif , Res. Lab., IBM Corp., Austin, TX, USA
pp. 145-149

Area/delay estimation for digital signal processor cores (PDF)

Y. Miyaoka , Dept. of Electron., Inf. & Commun. Eng., Waseda Univ., Tokyo, Japan
pp. 156-161

Equivalence checking of integer multipliers (PDF)

Jiunn-Chern Chen , Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 169-174

An efficient solution to the storage correspondence problem for large sequential circuits (PDF)

Wanlin Cao , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 181-186

A 3-step approach for performance-driven whole-chip routing (PDF)

Yih-Chih Chou , Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 187-191

Memory-efficient interconnect optimization (PDF)

Minghorng Lai , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 198-202

Balanced truncation with spectral shaping for RLC interconnects (PDF)

P. Heydari , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 203-208

On the minimization of SOPs for bi-decomposable functions (PDF)

T. Sasao , Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Fukuoka, Japan
pp. 219-224

A new technology mapping for CPLD under the time constraint (PDF)

Jae-Jin Kim , Dept. of Electron. Eng., Chongju Univ., South Korea
pp. 235-238

Power optimization and management in embedded systems (PDF)

M. Pedram , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 239-244

Low power techniques for address encoding and memory allocation (PDF)

Wei-Chung Cheng , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 245-250

The Tangram framework: asynchronous circuits for low power (PDF)

J. Kessels , Philips Res. Lab., Eindhoven, Netherlands
pp. 255-260

A pipelined ADC macro design for multiple applications (PDF)

K. Tani , Microelectron. Res. Center, Sanyo Electr. Co. Ltd., Gifu, Japan
pp. 269-274

A dynamically phase adjusting PLL with a variable delay (PDF)

T. Yasuda , Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan
pp. 275-280

A mixed-signal simulator for VHDL-AMS (PDF)

Xiao Liyi , Microelectron. Center, Harbin Inst. of Technol., China
pp. 287-291

Low power design challenges for the decade (PDF)

S. Borkar , Microprocessor Res. Labs., Intel Corp., Hillsboro, OR, USA
pp. 293-296

An on-chip 96.5% current efficiency CMOS linear regulator (PDF)

K. Sunaga , Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan
pp. 297-301

Reducing cache energy through dual voltage supply (PDF)

V.G. Moshnyaga , Dept. of Electr. & Comput. Sci., Fukuoka Univ., Japan
pp. 302-305

Trace-driven system-level power evaluation of system-on-a-chip peripheral cores (PDF)

T.D. Givargis , Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
pp. 306-311

Towards the logic defect diagnosis for partial-scan designs (PDF)

Shi-Yu Huang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 313-318

Processor-programmable memory BIST for bus-connected embedded memories (PDF)

Ching-Hong Tsai , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 325-330

Timed circuits: a new paradigm for high-speed design (PDF)

C.J. Myers , Dept. of Electr. Eng., Utah Univ., Salt Lake City, UT, USA
pp. 335-340

Formal verification of pulse-mode asynchronous circuits (PDF)

Xiaohua Kong , Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada
pp. 347-352

A statistical static timing analysis considering correlations between delays (PDF)

S. Tsukiyama , Dept. of Electr. Electron. & Comput. Eng., Chuo Univ., Tokyo, Japan
pp. 353-358

Post-layout transistor sizing for power reduction in cell-based design (PDF)

M. Hashimoto , Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan
pp. 359-365

Improved crosstalk modeling for noise constrained interconnect optimization (PDF)

J. Gong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 373-378

An efficient analytical model of coupled on-chip RLC interconnects (PDF)

Liang Yin , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 385-390

RSA cryptosystem design based on the Chinese remainder theorem (PDF)

Chung-Hsien Wu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 391-395

Speech recognition chip for monosyllables (PDF)

K. Nakamura , Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
pp. 396-399

Low power implementation of a turbo-decoder on programmable architectures (PDF)

F. Gilbert , Dept. of Electr. Eng. & Inf. Technol., Kaiserslautern Univ., Germany
pp. 400-403

New directions in compiler technology for embedded systems (PDF)

N. Dutt , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 409-414

A formal approach to component based development of synchronous programs (PDF)

P.S. Roop , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 421-424

Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits (PDF)

N. Sretasereekul , Res. Center for Adv. Sci. & Technol., Tokyo Univ., Japan
pp. 437-442

Design technology productivity in the DSM era (PDF)

A.B. Kahng , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 443-448

Low-power high-level synthesis using latches (PDF)

Wooseung Yang , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
pp. 462-465

Improved alternative wiring scheme applying dominator relationship (PDF)

Chin-Ngai Sze , Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Shatin, China
pp. 473-478

Design rewiring based on diagnosis techniques (PDF)

A. Veneris , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 479-484

A computer aided engineering system for memory BIST (PDF)

Chauchin Su , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
pp. 492-495

Slicing floorplan with clustering constraints (PDF)

W.S. Yuen , Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Shatin, China
pp. 503-508

Module placement with boundary constraints using the sequence-pair representation (PDF)

Jianbang Lai , Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
pp. 515-520

Toward better wireload models in the presence of obstacles (PDF)

Chung-Kuan Cheng , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 527-532

On-chip interconnections: impact of adjacent lines on timing (PDF)

Deschacht , Lab. d'Inf. de Robotique et de Microelectron., Montpellier, France
pp. 539-544

Short circuit power estimation of static CMOS circuits (PDF)

Seung-Ho Jung , Dept. of Comput., Soongsil Univ., Seoul, South Korea
pp. 545-549

Coarse grain reconfigurable architectures (PDF)

R. Hartenstein , Dept. of Comput. Sci., Kaiserslautern Univ., Germany
pp. 564-569

Efficient global fanout optimization algorithms (PDF)

R. Murgai , Fujitsu Labs. of America Inc., CA, USA
pp. 571-576

Timing driven gate duplication in technology independent phase (PDF)

A. Srivastava , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 577-582

On speeding up extended finite state machines using catalyst circuitry (PDF)

Shi-Yu Huang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 583-588

Integrated power supply planning and floorplanning (PDF)

I-Min Liu , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 589-594

Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points (PDF)

A.H. Ajami , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 595-600

VLSI block placement using less flexibility first principles (PDF)

Sheqin Dong , Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
pp. 601-604

Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders (PDF)

Youngtae Kim , Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
pp. 622-627

RPack: routability-driven packing for cluster-based FPGAs (PDF)

E. Bozorgzadeh , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 629-634

Power minimization in LUT-based FPGA technology mapping (PDF)

Zhi-Hong Wang , Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
pp. 635-640

High-level synthesis under multi-cycle interconnect delay (PDF)

Jinhwan Jeon , Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., South Korea
pp. 662-667

Author index (PDF)

pp. 669-674
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