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Proceedings of IEEE International Conference on Application Specific Array Processors (ASSAP'94) (1994)
San Francisco, CA
Aug. 22, 1994 to Aug. 24, 1994
ISSN: 1063-6862
ISBN: 0-8186-6517-3
TABLE OF CONTENTS

Data alignment of loop nests without nonlocal communications (PDF)

Weijia Shang , Dept. of Comput. Eng., Santa Clara Univ., CA, USA
Zhongliang Shu , Dept. of Comput. Eng., Santa Clara Univ., CA, USA
pp. 439-450

Loop transformation methodology for fixed-rate video, image and telecom processing applications (PDF)

F. Catthoor , IMEC, Leuven, Belgium
W. Geurts , IMEC, Leuven, Belgium
H. De Man , IMEC, Leuven, Belgium
pp. 427-438

A dynamically reconfigurable wavefront array architecture for evaluation of expressions (PDF)

R.W. Hartenstein , Kaiserslautern Univ., Germany
R. Kress , Kaiserslautern Univ., Germany
H. Reinig , Kaiserslautern Univ., Germany
pp. 404-414

An efficient VLSI architecture for digital geometry (PDF)

R. Lin , Dept. of Comput. Sci., State Univ. of New York, Genesco, NY, USA
pp. 392-403

A parallel DSP-based neural network emulator with CMOS VLSI packet switching hardware (PDF)

M. Schwarz , Fraunhofer-Inst. of Microelectron. Circuits & Syst., Duisberg, Germany
B.J. Hosticka , Fraunhofer-Inst. of Microelectron. Circuits & Syst., Duisberg, Germany
M. Kesper , Fraunhofer-Inst. of Microelectron. Circuits & Syst., Duisberg, Germany
P. Richert , Fraunhofer-Inst. of Microelectron. Circuits & Syst., Duisberg, Germany
M. Scholles , Fraunhofer-Inst. of Microelectron. Circuits & Syst., Duisberg, Germany
pp. 381-391

Constant-time triangulation problems on reconfigurable meshes (PDF)

V. Bokka , Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
H. Gurla , Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
S. Olariu , Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
J.L. Schwing , Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
pp. 357-368

Access and alignment of arrays for a bidimensional parallel memory (PDF)

C. Verdier , Telecom Paris Univ., France
E. Boutillon , Telecom Paris Univ., France
A. Lafage , Telecom Paris Univ., France
pp. 346-356

A SIMD solution to the sequence comparison problem on the MGAP (PDF)

M. Borah , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.S. Bajwa , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
S. Hannenhalli , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 336-345

Parallel processing of complex data using quaternion and pseudo-quaternion CORDIC algorithms (PDF)

Shen-Fu Hsiao , Inst. of Comput. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
pp. 324-335

A parallel system for photo realistic artificial scene rendering (PDF)

E.F. Deprettere , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
G.H. Hekstra , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Li-Shen Sheng , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 314-323

A sparse knapsack algo-tech-cuit and its synthesis (PDF)

R. Andonov , IRISA, Rennes, France
S. Rajopadhye , IRISA, Rennes, France
pp. 302-313

Designing systolic arrays for integer GCD computation (PDF)

T. Jebelean , RISC-LINZ, Linz, Austria
pp. 295-301

Synthesis of a class of data format converters with specified delays (PDF)

Jongwoo Bae , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
V.R. Prasanna , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Heonchul Park , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 283-294

A data path array with shared memory as core of a high performance DSP (PDF)

J. Kneip , Lab. fur Informationstechnol., Hannover Univ., Germany
K. Ronner , Lab. fur Informationstechnol., Hannover Univ., Germany
P. Pirsch , Lab. fur Informationstechnol., Hannover Univ., Germany
pp. 271-282

Architectures for lattice structure based orthonormal discrete wavelet transforms (PDF)

T.C. Denk , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
K.K. Parhi , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 259-270

A variable-precision interval arithmetic processor (PDF)

M.J. Schulte , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 248-258

On the injectivity of modular mappings (PDF)

H.J. Lee , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
J.A.B. Fortes , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 236-247

Optimal mapping of systolic algorithms by regular instruction shifts (PDF)

P. Clauss , Robert Schuman Univ., Strasbourg, France
pp. 224-235

Data compiling for systems of affine recurrence equations (PDF)

C. Mongenet , Dept. d'Inf., Univ. Louis Pasteur, Strasbourg, France
pp. 212-223

Regular array synthesis using ALPHA (PDF)

D.K. Wilde , IRISA, Rennes, France
O. Sie , IRISA, Rennes, France
pp. 200-211

A processor for calorimetry at the Large Hadron Collider in the FERMI project (PDF)

L. Dadda , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
pp. 188-199

A processor-time-minimal schedule for the standard tensor product algorithm (PDF)

C. Scheiman , Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
P. Cappello , Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
pp. 176-187

Verification of regular architectures using ALPHA: a case study (PDF)

C. Bezan , Dept. d'Inf., URF Sci. et Tech., Brest, France
pp. 164-175

Parallel architectures for computing the Hough transform and CT image reconstruction (PDF)

L. Lin , Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
V.K. Jain , Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
pp. 152-163

A fast pipelined FFT unit (PDF)

L. Breveglieri , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
V. Piuri , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
pp. 143-151

Analog VLSI arrays for morphological image processing (PDF)

T.G. Morris , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
S.P. DeWeerth , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 132-142

A systolic array for 2-D DFT and 2-D DCT (PDF)

Hyesook Lim , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 123-131

Register transfer modeling and simulation for array processors (PDF)

W.H. Chou , Dept. of Electr. Eng., Princeton Univ., NJ, USA
S.Y. Kung , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 111-122

Optimal synthesis of application specific heterogeneous pipelined multiprocessors (PDF)

J.C. DeSouza-Batista , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
A.C. Parker , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 99-110

A methodology for performance prediction of Sphinx I in multi-computer architectures (PDF)

C. Hernandez , Carnegie Mellon Univ., Pittsburgh, PA, USA
D. Siewiorek , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 87-98

Minimizing memory requirements in rate-optimal schedules (PDF)

R. Govindarajan , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 75-86

Rapid prototyping with programmable control paths (PDF)

R.S. Bajwa , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
C. Nagendra , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
P. Keltcher , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 69-74

Distributed control synthesis for data-dependent iterative algorithms (PDF)

Bongjin Jung , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Yongjin Jeong , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
W.P. Burleson , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 57-68

Automated design of DSP array processor chips (PDF)

J.V. McCanny , Inst. of Adv. Microelectron., Queen's Univ., Belfast, UK
Y. Hu , Inst. of Adv. Microelectron., Queen's Univ., Belfast, UK
M. Yan , Inst. of Adv. Microelectron., Queen's Univ., Belfast, UK
pp. 33-44

Algorithms and architectures for hierarchical compression of video (PDF)

M. Vishwanath , Comput. Sci. Lab., Xerox Palo Alto Res. Center, CA, USA
pp. 10-21

Fast linear Hough transform (PDF)

J.E. Vuillemin , Res. Lab., Digital Equipment Corp., Paris, France
pp. 1-9
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