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Proceedings of the International Conference on Application Specific Array Processors (1992)
Berkeley, CA, USA
Aug. 4, 1992 to Aug. 7, 1992
ISSN: 1063-6862
ISBN: 0-8186-2967-3
TABLE OF CONTENTS

High level software synthesis for signal processing systems (PDF)

S. Ritz , RWTH, Aachen, Germany
M. Pankert , RWTH, Aachen, Germany
H. Meyr , RWTH, Aachen, Germany
pp. 679-693

Fully static multiprocessor realization for real-time recursive DSP algorithms (PDF)

Duen-Jeng Wang , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Yu Hen Hu , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 664-678

Efficient scheduling methods for partitioned systolic algorithms (PDF)

P. Kuchibhotla , Dept. of Syst. Sci., California San Diego, La Jolla, CA, USA
pp. 649-663

Optimal design of lower dimensional processor arrays for uniform recurrences (PDF)

K.N. Ganapathy , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
B.W. Wah , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 636-648

Scheduling partitions in systolic algorithms (PDF)

A. Suarez , Dept. d'Arquitectura de Comput., Univ. Politecnica de Catalunya, Barcelona, Spain
J.M. Llaberia , Dept. d'Arquitectura de Comput., Univ. Politecnica de Catalunya, Barcelona, Spain
A. Fernandez , Dept. d'Arquitectura de Comput., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 619-633

Programming systolic arrays (PDF)

R. Hughey , California Univ., Santa Cruz, CA, USA
pp. 604-618

Compilation of narrowband spectral detection systems for linear MIMD machines (PDF)

H. Printz , Digital Equipment Corp., Rueil-Malmaison, France
pp. 589-603

Transformation techniques for serial array design (PDF)

W.W.C. Luk , Oxford Univ., Comput. Lab., UK
pp. 574-588

Mapping locally recursive SEGs upon a multiprocessor system in a ring network (PDF)

Wonyong Sung , Dept. of Control & Instrum. Eng., Seoul Nat. Univ., South Korea
pp. 560-573

Parallel architecture for a pel-recursive motion estimation algorithm (PDF)

E.D. Frimout , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
J.N. Driessen , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
E.F. Deprettere , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 551-558

Associative information processing: algorithms and system (PDF)

W. Poechmueller , Inst. for Microelectron. Syst., Darmstadt Univ. of Technol., Germany
A. Koenig , Inst. for Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Glesner , Inst. for Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 538-550

Determining longest common subsequences of two sequences on a linear array of processors (PDF)

A. Mukherjee , Dept. of Comput. Sci., Univ. of Central Florida, Orlando, FL, USA
pp. 526-537

MAMACG: a tool for automatic mapping of matrix algorithms onto mesh array computational graphs (PDF)

Dinh Le , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
M. Ercegovac , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 511-525

Matrix computations in arrays of DSPs (PDF)

J. Moreno , Dept. de Ingenieria Electr., Concepcion Univ., Chile
M. Medina , Dept. de Ingenieria Electr., Concepcion Univ., Chile
pp. 496-510

Systolic architectures for finite-state vector quantization (PDF)

R.K. Kolagotla , Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
Shu-Sun Yu , Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
J.F. JaJa , Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
pp. 481-495

Fault tolerant matrix triangularization and solution of linear systems of equations (PDF)

P. Fitzpatrick , IFI Inst. of Adv. Microelectron., Nat. Microelectron. Res. Centre, Univ. Coll. Cork, Ireland
C.C. Murphy , IFI Inst. of Adv. Microelectron., Nat. Microelectron. Res. Centre, Univ. Coll. Cork, Ireland
pp. 469-480

A parallel sorting algorithm on an eight-neighbor processor array (PDF)

K. Tanno , Dept. of Electr. & Inf. Eng., Yamagata Univ., Japan
T. Takeda , Dept. of Electr. & Inf. Eng., Yamagata Univ., Japan
pp. 456-468

Interval-related problems on reconfigurable meshes (PDF)

S. Olariu , Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
J.L. Schwing , Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
Jingyuan Zhang , Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
pp. 445-455

A systolic rank revealing QR algorithm (PDF)

F. Lorenzelli , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
K. Yao , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
T.F. Chan , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
P.C. Hansen , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 430-444

A method to synthesize modular systolic arrays with local broadcast facility (PDF)

T. Risset , Lab. de l'Inf. du Parallelisme, Ecole Normale Superieure de Lyon, France
pp. 415-428

A systolic array chip for robot inverse dynamics computation (PDF)

M. Rahman , VLSI Technology, Inc., Pompano Beach, FL, USA
pp. 400-414

An architecture for tree search based vector quantization for single chip implementation (PDF)

Heonchul Park , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
V.K. Prasanna , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Cho-Li Wang , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 385-399

High-speed VLSI architectures for soft-output Viterbi decoding (PDF)

O. Joeressen , RWTH Aachen, Germany
M. Vaupel , RWTH Aachen, Germany
H. Meyr , RWTH Aachen, Germany
pp. 373-384

The Sarnoff Engine: a massively parallel computer for high definition system simulation (PDF)

S. Knight , David Sarnoff Res. Center, Prrinceton, NJ, USA
D. Chin , David Sarnoff Res. Center, Prrinceton, NJ, USA
H. Taylor , David Sarnoff Res. Center, Prrinceton, NJ, USA
J. Peters , David Sarnoff Res. Center, Prrinceton, NJ, USA
pp. 342-356

Architecture and realization of a multi signal processor system (PDF)

A. Gunzinger , Electron. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
U. Muller , Electron. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
W. Scott , Electron. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
B. Baumle , Electron. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
P. Kohler , Electron. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
W. Guggenbuhl , Electron. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
pp. 327-340

Application and packaging of the AT&T DSP3 parallel signal processor (PDF)

R.R. Shively , AT&T Bell Labs., Whippany, NJ, USA
L.J. Wu , AT&T Bell Labs., Whippany, NJ, USA
pp. 316-326

Constant capacity signal flow signal processor architecture benchmark (PDF)

H. Habereder , Hughes Aircraft Co., Fullerton, CA, USA
R.L. Harrison , Hughes Aircraft Co., Fullerton, CA, USA
pp. 303-315

Heterogeneous digital signal processing systems for sonar (PDF)

T.E. Curtis , Underwater Sensors Dept., Defence Res. Agency, Portland, UK
pp. 294-302

Some low power implementations of DSP algorithms (PDF)

J.B. Evans , Dept. of Electr. & Comput. Eng., Kansas Univ., Lawrence, KS, USA
Bede Liu , Dept. of Electr. & Comput. Eng., Kansas Univ., Lawrence, KS, USA
pp. 269-276

Advanced technology for improved signal processor efficiency (PDF)

E.E. Swartzlander , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 257-268

On metrics of 'super performance' (signal processing systems) (PDF)

Y.S. Wu , Naval Res. Lab., Washington, DC, USA
pp. 248-256

Algorithms and architectures for high performance recursive filtering (PDF)

S.E. McQuillan , Dept. of Electr. & Electron. Eng., Queen's Univ. of Belfast, UK
J.V. McCanny , Dept. of Electr. & Electron. Eng., Queen's Univ. of Belfast, UK
pp. 230-244

Discrete wavelet transforms in VLSI (PDF)

M. Vishwanath , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
pp. 218-229

Deterministic Boltzmann machine VLSI can be scaled using multi-chip modules (PDF)

M. Murray , Dept. of Electr. Eng., Stanford Univ., CA, USA
J.B. Burr , Dept. of Electr. Eng., Stanford Univ., CA, USA
pp. 206-217

Implementing a family of high performance, micrograined architectures (PDF)

R.M. Owens , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
T.P. Kelliher , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
M. Vishwanath , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
R.S. Bajwa , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
pp. 191-205

SPERT: a VLIW/SIMD microprocessor for artificial neural network computations (PDF)

K. Asanovic , Int. Comput. Sci. Inst., Berkeley, CA, USA
J. Beck , Int. Comput. Sci. Inst., Berkeley, CA, USA
B.E.D. Kingsbury , Int. Comput. Sci. Inst., Berkeley, CA, USA
P. Kohn , Int. Comput. Sci. Inst., Berkeley, CA, USA
N. Morgan , Int. Comput. Sci. Inst., Berkeley, CA, USA
pp. 178-190

Pipelining: just another transformation (PDF)

M. Potkonjak , C&C Res. Labs., NEC, Princeton, NJ, USA
pp. 163-175

ARREST: an interactive graphic analysis tool for VLSI arrays (PDF)

W. Burleson , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Bongjin Jung , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 149-162

An integrated system for rapid prototyping of high performance algorithm specific data paths (PDF)

D.C. Chen , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
L.M. Guerra , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
E.H. Ng , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 134-148

Synthesis of application-specific multiprocessor systems including memory components (PDF)

S. Prakash , Univ. of Southern California, Los Angeles, CA, USA
A.C. Parker , Univ. of Southern California, Los Angeles, CA, USA
pp. 118-132

A reconfigurable processor array with routing LSIs and general purpose DSPs (PDF)

J. Levison , C&C Syst. Res. Labs., NEC Corp., Kawasaki, Japan
I. Kuroda , C&C Syst. Res. Labs., NEC Corp., Kawasaki, Japan
T. Nishitani , C&C Syst. Res. Labs., NEC Corp., Kawasaki, Japan
pp. 102-116

On partitioning of multistage algorithms and design of intermediate memories (PDF)

M. Sauer , Inst. for Network Theory & Circuit Design, Tech. Univ. Munich, Germany
E. Bernard , Inst. for Network Theory & Circuit Design, Tech. Univ. Munich, Germany
J.A. Nossek , Inst. for Network Theory & Circuit Design, Tech. Univ. Munich, Germany
pp. 89-101

A projective geometry architecture for scientific computation (PDF)

B.S. Amrutur , AT&T Bell Labs., Murray Hill, NJ, USA
R. Joshi , AT&T Bell Labs., Murray Hill, NJ, USA
N.K. Karmarkar , AT&T Bell Labs., Murray Hill, NJ, USA
pp. 64-80

On systolic mapping of multi-stage algorithms (PDF)

Yin-Tsung Hwang , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Yu Hen Hu , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 47-61

Linear scheduling is close to optimality (PDF)

A. Darte , Lab. LIP-IMAG, Ecole Normale Superieure de Lyon, France
L. Khachiyan , Lab. LIP-IMAG, Ecole Normale Superieure de Lyon, France
Y. Robert , Lab. LIP-IMAG, Ecole Normale Superieure de Lyon, France
pp. 37-46

Hierarchical scheduling of DSP programs onto multiprocessors for maximum throughput (PDF)

Phu Hoang , Dept. of Electr. Eng., California Univ., Berkeley, CA, USA
J. Rabaey , Dept. of Electr. Eng., California Univ., Berkeley, CA, USA
pp. 21-36

A transformative approach to the partitioning of processor arrays (PDF)

J. Teich , Inst. of Microelectron., Univ. of Saarland, Saarbrucken, Germany
L. Thiele , Inst. of Microelectron., Univ. of Saarland, Saarbrucken, Germany
pp. 4-20
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