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Proceedings of the International Conference on Application Specific Array Processors (1990)
Princeton, NJ, USA
Sept. 5, 1990 to Sept. 7, 1990
ISBN: 0-8186-9089-5
TABLE OF CONTENTS

Calculus of space-optimal mappings of systolic algorithms on processor arrays (PDF)

P. Clauss , Lab. d'Inf. de Besancon, Univ. de Franche-Comte, France
pp. 4-18

A processor-time minimal systolic array for transitive closure (PDF)

C.J. Scheiman , Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
P.R. Cappello , Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
pp. 19-30

Systolic array implementation of nested loop programs (PDF)

J. Bu , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
E.F. Deprettere , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 31-42

The bit-serial systolic back-projection engine (BSSBPE) (PDF)

R. Bayford , Middlesex Polytech., London, UK
pp. 43-54

A database machine based on surrogate files (PDF)

S.M. Chung , Dept. of Comput. Sci. & Eng., Wright State Univ., Dayton, OH, USA
pp. 55-66

Systolic architectures for decoding Reed-Solomon codes (PDF)

J. Nelson , Dept. of Electron. & Comput. Eng., Limerick Univ., Ireland
A. Rahman , Dept. of Electron. & Comput. Eng., Limerick Univ., Ireland
E. McQuade , Dept. of Electron. & Comput. Eng., Limerick Univ., Ireland
pp. 67-77

Mapping high-dimension wavefront computations to silicon (PDF)

C.-M. Wu , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
pp. 78-89

Systolic architecture for 2-D rank order filtering (PDF)

J.-N. Hwang , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
J.-M. Jong , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 90-99

Scheduling affine parameterized recurrences by means of (PDF)

C. Mauras , IRISA, Rennes, France
P. Quinton , IRISA, Rennes, France
pp. 100-110

Recursive algorithms for AR spectral estimation and their array realizations (PDF)

Liu Chi-Min , Inst. of Electron., Nat. Chiao Tung Univ., Taiwan
Jen Chein-Wei , Inst. of Electron., Nat. Chiao Tung Univ., Taiwan
pp. 121-132

Analysing parametrised designs by non-standard interpretation (PDF)

W. Luk , Computing Lab., Oxford Univ., UK
pp. 133-144

Systolic VLSI compiler (SVC) for high performance vector quantisation chips (PDF)

Y. Hu , Dept. of Electr. & Electron. Eng., Queen's Univ. of Belfast, UK
J.V. McCanny , Dept. of Electr. & Electron. Eng., Queen's Univ. of Belfast, UK
M. Yan , Dept. of Electr. & Electron. Eng., Queen's Univ. of Belfast, UK
pp. 145-155

Extensions to linear mapping for regular arrays with complex processing elements (PDF)

J. Rosseel , IMEC, Leuven, Belgium
F. Catthoor , IMEC, Leuven, Belgium
H. De Man , IMEC, Leuven, Belgium
pp. 156-167

Design of run-time fault-tolerant arrays of self-checking processing elements (PDF)

J. Franzen , Inst. fuer Theor. Nachrichtentech. und Informationsverarbeitung, Hannover Univ., Germany
pp. 168-179

GRAPE: a special-purpose computer for N-body problems (PDF)

J. Makino , Tokyo Univ., Japan
T. Ito , Tokyo Univ., Japan
T. Ebisuzaki , Tokyo Univ., Japan
D. Sugimoto , Tokyo Univ., Japan
pp. 180-189

Reconfigurable vector register windows for fast matrix computation on the orthogonal multiprocessor (PDF)

D.K. Panda , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
K. Hwang , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 202-213

Massively parallel architecture: application to neural net emulation and image reconstruction (PDF)

D. Lattard , IMAG-LGI, Grenoble, France
B. Faure , IMAG-LGI, Grenoble, France
G. Mazare , IMAG-LGI, Grenoble, France
pp. 214-225

Mapping algorithms onto the TUT cellular array processor (PDF)

J. Viitanen , Tampere Univ. of Technol., Finland
T. Korpiharju , Tampere Univ. of Technol., Finland
J. Takala , Tampere Univ. of Technol., Finland
H. Kliminkinen , Tampere Univ. of Technol., Finland
pp. 235-246

A 3-D wafer scale architecture for early vision processing (PDF)

S.T. Toborg , Hughes Res. Lab., Malibu, CA, USA
pp. 247-258

Algorithmic mapping of neural network models onto parallel SIMD machines (PDF)

V.K.P. Kumar , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 259-271

Implementation of systolic algorithms using pipelined functional units (PDF)

M. Valero-Garcia , Dept. Arquitectura de Computadores, Univ. Politecnica de Catalunya, Barcelona, Spain
J.J. Navarro , Dept. Arquitectura de Computadores, Univ. Politecnica de Catalunya, Barcelona, Spain
J.M. Llaberia , Dept. Arquitectura de Computadores, Univ. Politecnica de Catalunya, Barcelona, Spain
M. Valero , Dept. Arquitectura de Computadores, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 272-283

Array processing on finite polynomial rings (PDF)

N. Wigley , Windsor Univ., Ont., Canada
G.A. Jullien , Windsor Univ., Ont., Canada
pp. 284-295

The RAP: a ring array processor for layered network calculations (PDF)

N. Morgan , Int. Comput. Sci. Inst., Berkeley, CA, USA
J. Beck , Int. Comput. Sci. Inst., Berkeley, CA, USA
P. Kohn , Int. Comput. Sci. Inst., Berkeley, CA, USA
J. Bilmes , Int. Comput. Sci. Inst., Berkeley, CA, USA
E. Allman , Int. Comput. Sci. Inst., Berkeley, CA, USA
J. Beer , Int. Comput. Sci. Inst., Berkeley, CA, USA
pp. 296-308

Linear arrays for residue mappers (PDF)

Z.B. Sarkari , LSI Logic Corp., Milpitas, CA, USA
pp. 309-316

A fault-tolerant two-dimensional sorting network (PDF)

J.G. Krammer , Tech. Univ., Munich, Germany
H. Arif , Tech. Univ., Munich, Germany
pp. 317-328

Channel complexity analysis for reconfigurable VLSI/WSI processor arrays (PDF)

P.K. Rhee , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
J.H. Kim , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
pp. 329-340

Digit-serial DSP architectures (PDF)

K.K. Parhi , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
C.Y. Wang , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 341-351

PASIC. A sensor/processor array for computer vision (PDF)

K. Chen , Linkoping Univ., Sweden
P.E. Danielsson , Linkoping Univ., Sweden
A. Astrom , Linkoping Univ., Sweden
pp. 352-366

An analog VLSI array processor for classical and connectionist AI (PDF)

J.W. Mills , Indiana Univ., Bloomington, IN, USA
C.A. Daffinger , Indiana Univ., Bloomington, IN, USA
pp. 367-378

Systolic two-port adaptor for high performance wave digital filtering (PDF)

R.J. Singh , Dept. of Electr. & Electron. Eng., Queen's Univ., Belfast, UK
J.V. McCanny , Dept. of Electr. & Electron. Eng., Queen's Univ., Belfast, UK
pp. 379-388

An improved multilayer neural model and array processor implementation (PDF)

C.C. Chiang , Dept. of Comput. Sci. & Inf. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
H.C. Fu , Dept. of Comput. Sci. & Inf. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
pp. 389-400

Reconfiguration of FFT arrays: a flow-driven approach (PDF)

A. Antola , Dipartimento di Elettronica, Politechnico di Milano, Italy
N. Scarabottolo , Dipartimento di Elettronica, Politechnico di Milano, Italy
pp. 401-413

Towards the automated design of application specific array processors (ASAPs) (PDF)

A.P. Marriott , Dept. of Electr. Eng. & Electron., Univ. of Manchester, Inst. of Sci. & Technol., UK
pp. 414-425

Fault-tolerant array processors using N-and-half-track switches (PDF)

J.S.N. Jean , Dept. of Comput. Sci. & Eng., Wright State Univ., Dayton, OH, USA
pp. 426-437

Domain flow and streaming architectures (PDF)

E. Theodore , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
L. Omtzigt , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
pp. 438-447

An improved systolic extended Euclidean algorithm for Reed-Solomon decoding: design and implementation (PDF)

R. Doyle , Nat. Microelectron. Res. Centre, Univ. Coll., Cork, Ireland
P. Fitzpatrick , Nat. Microelectron. Res. Centre, Univ. Coll., Cork, Ireland
pp. 448-456

Digit-serial VLSI microarchitecture (PDF)

S.G. Smith , VLSI Technol., Valbonne, France
J.G. Payne , VLSI Technol., Valbonne, France
R.W. Morgan , VLSI Technol., Valbonne, France
pp. 457-468

CMOS VLSI Lukasiewicz logic arrays (PDF)

J.W. Mills , Dept. of Comput. Sci., Indiana Univ., Bloomington, IN, USA
C.A. Daffinger , Dept. of Comput. Sci., Indiana Univ., Bloomington, IN, USA
pp. 469-480

Dynamic systolic associative memory chip (PDF)

G.J. Lipovski , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 481-492

Designing specific systolic arrays with the API15C chip (PDF)

P. Frison , IRISA, Rennes, France
E. Gautrin , IRISA, Rennes, France
D. Lavenier , IRISA, Rennes, France
J.L. Scharbarg , IRISA, Rennes, France
pp. 505-517

A prototype for a fault tolerant parallel signal processor (PDF)

B.R. Musicus , Res. Lab. of Electron., MIT, Cambridge, MA, USA
pp. 518-529

Byte-serial convolvers (PDF)

L. Dadda , Dept. of Electron., Politecnico di Milano, Italy
pp. 530-541

A VLSI architecture for simplified arithmetic Fourier transform algorithm (PDF)

I.S. Reed , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
M.T. Shih , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
E. Hendon , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
pp. 542-553

Fine-grain system architectures for systolic emulation of neural algorithms (PDF)

U. Ramacher , SIEMENS AG, Munich, Germany
W. Raab , SIEMENS AG, Munich, Germany
pp. 554-566

A feedback concentrator for the Image Understanding Architecture (PDF)

D. Rana , Massachusetts Univ., Amherst, MA, USA
C.C. Weems , Massachusetts Univ., Amherst, MA, USA
pp. 579-590

A design methodology for fixed-size systolic arrays (PDF)

J. Bu , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
E.F. Deprettere , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
P. Dewilde , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 591-602

A formal design methodology for parallel architectures (PDF)

K.M. Elleithy , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
M.A. Bayoumi , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
pp. 603-614

A multiple-level heterogeneous architecture for image understanding (PDF)

D.B. Shu , Hughes Res. Lab., Malibu, CA, USA
J.G. Nash , Hughes Res. Lab., Malibu, CA, USA
pp. 615-627

Application specific VLSI architectures based on De Bruijn graphs (PDF)

D.K. Pradhan , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 628-640

A graph-based approach to map matrix algorithms onto local-access processor arrays (PDF)

J.H. Moreno , Dept. de Ingenieria Electr., Univ. de Concepcion, Chile
pp. 641-652

Application-specific coprocessor computer architecture (PDF)

Y. Chu , Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA
pp. 653-664

Embedding pyramids in array processors with pipelined busses (PDF)

Z. Guo , Dept. of Electr. Eng. & Comput. Sci., Pittsburgh Univ., PA, USA
R.G. Melhem , Dept. of Electr. Eng. & Comput. Sci., Pittsburgh Univ., PA, USA
pp. 665-676

Implementation of ANN on RISC processor array (PDF)

A. Hiraiwa , Sony Corp. Res. Lab., Kanagawa, Japan
M. Fujita , Sony Corp. Res. Lab., Kanagawa, Japan
S. Kurosu , Sony Corp. Res. Lab., Kanagawa, Japan
S. Arisawa , Sony Corp. Res. Lab., Kanagawa, Japan
M. Inoue , Sony Corp. Res. Lab., Kanagawa, Japan
pp. 677-688

Systolic-based computing machinery for radar signal processing studies (PDF)

S. Haykin , Commun. Res. Lab., McMaster Univ., Hamilton, Ont., Canada
P. Weber , Commun. Res. Lab., McMaster Univ., Hamilton, Ont., Canada
B. Cho , Commun. Res. Lab., McMaster Univ., Hamilton, Ont., Canada
T. Greenlay , Commun. Res. Lab., McMaster Univ., Hamilton, Ont., Canada
J. Orlando , Commun. Res. Lab., McMaster Univ., Hamilton, Ont., Canada
C. Deng , Commun. Res. Lab., McMaster Univ., Hamilton, Ont., Canada
R. Mann , Commun. Res. Lab., McMaster Univ., Hamilton, Ont., Canada
pp. 689-699

A systolic array for nonlinear adaptive filtering and pattern recognition (PDF)

J.G. McWhirter , R. Signals & Radar Establ., Malvern, UK
D.S. Broomhead , R. Signals & Radar Establ., Malvern, UK
T.J. Shepherd , R. Signals & Radar Establ., Malvern, UK
pp. 700-711

Parallel algorithm for traveling salesman problem on SIMD machines using simulated annealing (PDF)

C.S. Jeong , Dept. of Comput. Sci., Pohang Inst. of Sci. & Technol., South Korea
M.H. Kim , Dept. of Comput. Sci., Pohang Inst. of Sci. & Technol., South Korea
pp. 712-721

The design of a high-performance scalable architecture for image processing applications (PDF)

C.T. Gray , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
W. Liu , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
T. Hughes , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
R. Cavin , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 722-733

Testing a motion estimator array (PDF)

W.P. Marnane , Sch. of Electron. Eng. Sci., Univ. Coll. of North Wales, Bangor, UK
pp. 734-745

Spacetime-minimal systolic architectures for Gaussian elimination and the algebraic path problem (PDF)

A. Benaini , LIP-IMAG, Ecole Normale Superieure de Lyon, France
Y. Robert , LIP-IMAG, Ecole Normale Superieure de Lyon, France
pp. 746-757

Bit-level systolic algorithm for the symmetric eigenvalue problem (PDF)

J.-M. Delosme , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
pp. 770-781

A systolic array programming language (PDF)

P.S. Tseng , Bellcore, Morristown, NJ, USA
pp. 794-803
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