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Proceedings 1998 International Conference on Application of Concurrency to System Design (1998)
Fukushima, Japan
Mar. 23, 1998 to Mar. 26, 1998
ISBN: 0-8186-8350-3
Tutorial Papers

Logic and Functional Verification in a Commercial Semiconductor Environment (Abstract)

Jainendra Kumar , Advanced Systems Technology Lab, MOTOROLA Inc.
Carl Pixley , Advanced Systems Technology Lab, MOTOROLA Inc.
pp. 8

System-Level Design Models and Implementation Techniques (Abstract)

Luciano Lavagno , Dipartimento di Elettronica Politecnico di Torino
pp. 24
Hierarchical Models

Hierarchical Concurrent Finite State Machines in Ptolemy (Abstract)

Bilung Lee , University of California at Berkeley
Edward A. Lee , University of California at Berkeley
pp. 34

A Translation of Statecharts into Signal Approach of Time, Interoperability (Abstract)

J.R. Beauvais , IRISA, Campus de Beaulieu
R. Houdebine , IRISA, Campus de Beaulieu
P. Le Guernic , IRISA, Campus de Beaulieu
E. Rutten , IRISA, Campus de Beaulieu
T. Gautier , IRISA, Campus de Beaulieu
pp. 52
Hierarchical Verification

Verification of Parameterized Asynchronous Circuits: A Case Study (Abstract)

Tomohiro Yoneda , Tokyo Institute of Technology
Yutaka Ohtsuka , Tokyo Institute of Technology
Mart Saarepera , Tokyo Institute of Technology
pp. 64

Unbounded Verification Results by Finite-State Compositional Techniques: 10^any States and Beyond (Abstract)

Antti Valmari , Tampere University of Technology
Ilkka Kokkarinen , Tampere University of Technology
pp. 75
Systems with Timing

Formal Verification of Real-Time Software by Symbolic Model-Checker (Abstract)

Kazuhiro Nakamura , Nara Institute of Science and Technology
Satoshi Yamane , Nara Institute of Science and Technology
pp. 99

Integrating the Verification of Timing, Performance and Correctness Properties of Concurrent Systems (Abstract)

A. Cerone , University of South Australia
D.A. Kearney , University of South Australia
G. J. Milne , University of South Australia
pp. 109

Timing Extensions of STG Model and a Method to Simulate Timed STG Behavior in VHDL Environment (Abstract)

Michael V. Goncharov , Institute for Analytical Instrumentation of RAS
Alexander B. Smirnov , Institute for Analytical Instrumentation of RAS
Nikolai A. Starodoubtsev , Institute for Analytical Instrumentation of RAS
Ilya V. Klotchkov , St.-Petersburg State University,
pp. 120
PN-Based Verification

Efficient Approach to Symbolic State Exploration of Complex Parallel Controllers (Abstract)

K. Bilinski , Technical University of Zielona Gora
E.L. Dagless , University of Bristol, UK
pp. 132
High-Level Nets

Using Object-Oriented Algebraic Nets for the Reverse Engineering of Java Programs: A Case Study (Abstract)

Giovanna Di Marzo Serugendo , CUI, University of Geneva
Nicolas Guelfi , LGL-DI, Swiss Federal Institute of Technology
pp. 166
Hardware Verification
Panel Discussion
Algebraic Models and Languages

A True Concurrency Semantics for ET-LOTOS (Abstract)

Howard Bowman , University of Kent
Joost-Pieter Katoen , University of Erlangen-Nuernberg
pp. 228

Recursive Nets in the Box Algebra (Abstract)

Raymond Devillers , Universite Libre de Bruxelles
Maciej Koutny , University of Newcastle
pp. 239

A Presentation of Regular Languages in the Assumption - Commitment Framework (Abstract)

Swarup Mohalik , The Institute of Mathematical Sciences
R. Ramanujam , The Institute of Mathematical Sciences
pp. 250
Case Studies

Modeling and Analyzing Interorganizational Workflows (Abstract)

W.M.P. Van der Aalst , Eindhoven University of Technology
pp. 262

Traffic Lights - An AutoFocus Case Study (Abstract)

Franz Huber , Technische Universit?t M?nchen
Sascha Molterer , Technische Universit?t M?nchen
Bernhard Schätz , Technische Universit?t M?nchen
Oscar Slotosch , Technische Universit?t M?nchen
Alexander Vilbig , Technische Universit?t M?nchen
pp. 282

Author Index (PDF)

pp. 295
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